| Message ID | 20190812100216.34459-1-wen.he_1@nxp.com |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
| Series | None | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success |
Quoting Wen He (2019-08-12 03:02:16) > diff --git a/Documentation/devicetree/bindings/clock/fsl,plldig.txt b/Documentation/devicetree/bindings/clock/fsl,plldig.txt > new file mode 100644 > index 000000000000..29c5a6117809 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/fsl,plldig.txt > @@ -0,0 +1,26 @@ > +NXP QorIQ Layerscape LS1028A Display output interface Clock > +=========================================================== Can you convert this to YAML? > + > +Required properties: > + - compatible: shall contain "fsl,ls1028a-plldig" > + - reg: Physical base address and size of the block registers > + - #clock-cells: shall contain 1. As I said in the previous patch, this should probably be 0. Also, please order this before the driver in the patch series and thread your messages please. If you use git-send-email this is done for you pretty easily. > + - clocks: a phandle + clock-specifier pairs, here should be > + specify the reference clock of the system > + > +
> -----Original Message----- > From: Stephen Boyd <sboyd@kernel.org> > Sent: 2019年8月14日 2:30 > To: Mark Rutland <mark.rutland@arm.com>; Michael Turquette > <mturquette@baylibre.com>; Rob Herring <robh+dt@kernel.org>; Shawn Guo > <shawnguo@kernel.org>; Wen He <wen.he_1@nxp.com>; > devicetree@vger.kernel.org; linux-clk@vger.kernel.org; > linux-kernel@vger.kernel.org > Cc: Leo Li <leoyang.li@nxp.com>; liviu.dudau@arm.com; Wen He > <wen.he_1@nxp.com> > Subject: [EXT] Re: [v1 2/3] dt/bindings: clk: Add DT bindings for LS1028A > Display output interface > > Caution: EXT Email > > Quoting Wen He (2019-08-12 03:02:16) > > diff --git a/Documentation/devicetree/bindings/clock/fsl,plldig.txt > > b/Documentation/devicetree/bindings/clock/fsl,plldig.txt > > new file mode 100644 > > index 000000000000..29c5a6117809 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/clock/fsl,plldig.txt > > @@ -0,0 +1,26 @@ > > +NXP QorIQ Layerscape LS1028A Display output interface Clock > > +=========================================================== > > Can you convert this to YAML? Sure, no problem. > > > + > > +Required properties: > > + - compatible: shall contain "fsl,ls1028a-plldig" > > + - reg: Physical base address and size of the block registers > > + - #clock-cells: shall contain 1. > > As I said in the previous patch, this should probably be 0. Also, please order > this before the driver in the patch series and thread your messages please. If > you use git-send-email this is done for you pretty easily. Understand, Will prepare and send next version patch. Best Regards, Wen > > > + - clocks: a phandle + clock-specifier pairs, here should be > > + specify the reference clock of the system > > + > > +
diff --git a/Documentation/devicetree/bindings/clock/fsl,plldig.txt b/Documentation/devicetree/bindings/clock/fsl,plldig.txt new file mode 100644 index 000000000000..29c5a6117809 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/fsl,plldig.txt @@ -0,0 +1,26 @@ +NXP QorIQ Layerscape LS1028A Display output interface Clock +=========================================================== + +Required properties: + - compatible: shall contain "fsl,ls1028a-plldig" + - reg: Physical base address and size of the block registers + - #clock-cells: shall contain 1. + - clocks: a phandle + clock-specifier pairs, here should be + specify the reference clock of the system + + +Example: + +/ { + ... + + dpclk: clock-controller@f1f0000 { + compatible = "fsl,ls1028a-plldig"; + reg = <0x0 0xf1f0000 0x0 0xffff>; + #clock-cells = <1>; + clocks = <&osc_27m>; + }; + + ... +}; +
Add DT bindings documentmation for the Clock of the LS1028A Display output interface. Signed-off-by: Wen He <wen.he_1@nxp.com> --- .../devicetree/bindings/clock/fsl,plldig.txt | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/fsl,plldig.txt