gpio: cadence: Pass irqchip when adding gpiochip
diff mbox series

Message ID 20190809131804.20352-1-linus.walleij@linaro.org
State New
Headers show
Series
  • gpio: cadence: Pass irqchip when adding gpiochip
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Commit Message

Linus Walleij Aug. 9, 2019, 1:18 p.m. UTC
We need to convert all old gpio irqchips to pass the irqchip
setup along when adding the gpio_chip. For more info see
drivers/gpio/TODO.

For chained irqchips this is a pretty straight-forward
conversion.

Cc: Jan Kotas <jank@cadence.com>
Cc: Thierry Reding <treding@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
Hi Jan, it'd be great if you could test/review this
patch.
---
 drivers/gpio/gpio-cadence.c | 36 +++++++++++++++++++++---------------
 1 file changed, 21 insertions(+), 15 deletions(-)

Comments

Jan Kotas Aug. 12, 2019, 9:53 a.m. UTC | #1
> On 9 Aug 2019, at 15:18, Linus Walleij <linus.walleij@linaro.org> wrote:
> 
> We need to convert all old gpio irqchips to pass the irqchip
> setup along when adding the gpio_chip. For more info see
> drivers/gpio/TODO.
> 
> For chained irqchips this is a pretty straight-forward
> conversion.
> 
> Cc: Jan Kotas <jank@cadence.com>
> Cc: Thierry Reding <treding@nvidia.com>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> ---
> Hi Jan, it'd be great if you could test/review this
> patch.

Everything seems to be OK in my tests.

Regards,
Jan
Linus Walleij Aug. 14, 2019, 8:37 a.m. UTC | #2
On Mon, Aug 12, 2019 at 11:53 AM Jan Kotas <jank@cadence.com> wrote:
> > On 9 Aug 2019, at 15:18, Linus Walleij <linus.walleij@linaro.org> wrote:
> >
> > We need to convert all old gpio irqchips to pass the irqchip
> > setup along when adding the gpio_chip. For more info see
> > drivers/gpio/TODO.
> >
> > For chained irqchips this is a pretty straight-forward
> > conversion.
> >
> > Cc: Jan Kotas <jank@cadence.com>
> > Cc: Thierry Reding <treding@nvidia.com>
> > Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> > ---
> > Hi Jan, it'd be great if you could test/review this
> > patch.
>
> Everything seems to be OK in my tests.

Thanks, recorded as Tested-by and applied!

Yours,
Linus Walleij

Patch
diff mbox series

diff --git a/drivers/gpio/gpio-cadence.c b/drivers/gpio/gpio-cadence.c
index 712ae212b0b4..a4d3239d2594 100644
--- a/drivers/gpio/gpio-cadence.c
+++ b/drivers/gpio/gpio-cadence.c
@@ -214,27 +214,33 @@  static int cdns_gpio_probe(struct platform_device *pdev)
 		goto err_revert_dir;
 	}
 
-	ret = devm_gpiochip_add_data(&pdev->dev, &cgpio->gc, cgpio);
-	if (ret < 0) {
-		dev_err(&pdev->dev, "Could not register gpiochip, %d\n", ret);
-		goto err_disable_clk;
-	}
-
 	/*
-	 * irq_chip support
+	 * Optional irq_chip support
 	 */
 	irq = platform_get_irq(pdev, 0);
 	if (irq >= 0) {
-		ret = gpiochip_irqchip_add(&cgpio->gc, &cdns_gpio_irqchip,
-					   0, handle_level_irq,
-					   IRQ_TYPE_NONE);
-		if (ret) {
-			dev_err(&pdev->dev, "Could not add irqchip, %d\n",
-				ret);
+		struct gpio_irq_chip *girq;
+
+		girq = &cgpio->gc.irq;
+		girq->chip = &cdns_gpio_irqchip;
+		girq->parent_handler = cdns_gpio_irq_handler;
+		girq->num_parents = 1;
+		girq->parents = devm_kcalloc(&pdev->dev, 1,
+					     sizeof(*girq->parents),
+					     GFP_KERNEL);
+		if (!girq->parents) {
+			ret = -ENOMEM;
 			goto err_disable_clk;
 		}
-		gpiochip_set_chained_irqchip(&cgpio->gc, &cdns_gpio_irqchip,
-					     irq, cdns_gpio_irq_handler);
+		girq->parents[0] = irq;
+		girq->default_type = IRQ_TYPE_NONE;
+		girq->handler = handle_level_irq;
+	}
+
+	ret = devm_gpiochip_add_data(&pdev->dev, &cgpio->gc, cgpio);
+	if (ret < 0) {
+		dev_err(&pdev->dev, "Could not register gpiochip, %d\n", ret);
+		goto err_disable_clk;
 	}
 
 	cgpio->bypass_orig = ioread32(cgpio->regs + CDNS_GPIO_BYPASS_MODE);