From patchwork Fri Aug 9 13:05:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frederic Barrat X-Patchwork-Id: 1144693 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 464lrg38f4z9sND for ; Fri, 9 Aug 2019 23:07:15 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 464lrg1WjxzDqgZ for ; Fri, 9 Aug 2019 23:07:15 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=linux.ibm.com (client-ip=148.163.158.5; helo=mx0a-001b2d01.pphosted.com; envelope-from=fbarrat@linux.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 464lq20RVpzDqdX for ; Fri, 9 Aug 2019 23:05:49 +1000 (AEST) Received: from pps.filterd (m0098420.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x79D2XDn133158 for ; Fri, 9 Aug 2019 09:05:41 -0400 Received: from e06smtp04.uk.ibm.com (e06smtp04.uk.ibm.com [195.75.94.100]) by mx0b-001b2d01.pphosted.com with ESMTP id 2u98xh1bd3-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Fri, 09 Aug 2019 09:05:40 -0400 Received: from localhost by e06smtp04.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Fri, 9 Aug 2019 14:05:37 +0100 Received: from d06av24.portsmouth.uk.ibm.com (d06av24.portsmouth.uk.ibm.com [9.149.105.60]) by b06cxnps4075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x79D5a6F58654926 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 9 Aug 2019 13:05:36 GMT Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 131B54203F; Fri, 9 Aug 2019 13:05:36 +0000 (GMT) Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id CF01742042; Fri, 9 Aug 2019 13:05:35 +0000 (GMT) Received: from pic2.home (unknown [9.145.165.217]) by d06av24.portsmouth.uk.ibm.com (Postfix) with ESMTP; Fri, 9 Aug 2019 13:05:35 +0000 (GMT) From: Frederic Barrat To: skiboot@lists.ozlabs.org, andrew.donnellan@au1.ibm.com, clombard@linux.ibm.com, arbab@linux.ibm.com, alistair@popple.id.au Date: Fri, 9 Aug 2019 15:05:34 +0200 X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190809130534.9152-1-fbarrat@linux.ibm.com> References: <20190809130534.9152-1-fbarrat@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 19080913-0016-0000-0000-0000029CBABE X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19080913-0017-0000-0000-000032FCC30C Message-Id: <20190809130534.9152-4-fbarrat@linux.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-08-09_03:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1906280000 definitions=main-1908090133 Subject: [Skiboot] [PATCH v2 4/4] npu3: Register virtual PHBs with static IDs X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Assigning opal IDs to virtual PHBs dynamically may lead to userland seeing the PCI domain ID for an adapter vary when adding or removing another adapter (GPU or opencapi). This patch switches to using static opal IDs for virtual PHBs, based on their ibm,phb-index property, which was made static by a previous patch. Note that the PCI domain IDs will increase on the second chip (or more, if we had more) because we now reserve 16 IDs per chip for PHBs. This affects Axone only. We don't change anything on P9 and npu2, to avoid altering how domain IDs have been shown on already GA'd platforms. Signed-off-by: Frederic Barrat Reviewed-by: Reza Arbab Reviewed-by: Andrew Donnellan --- Changelog: v2: new patch: use static opal IDs for virtual PHBs on axone hw/npu3-nvlink.c | 3 ++- include/npu3.h | 6 ++++++ include/phb4.h | 7 ++++++- 3 files changed, 14 insertions(+), 2 deletions(-) diff --git a/hw/npu3-nvlink.c b/hw/npu3-nvlink.c index 99608368..af2dda9f 100644 --- a/hw/npu3-nvlink.c +++ b/hw/npu3-nvlink.c @@ -904,7 +904,8 @@ static void npu3_create_phb(struct npu3 *npu) assert(phb->dt_node); list_head_init(&phb->virt_devices); - pci_register_phb(phb, OPAL_DYNAMIC_PHB_ID); + pci_register_phb(phb, npu3_get_opal_id(npu->chip_id, + npu3_get_phb_index(npu->index))); npu3_create_phb_slot(npu); npu3_ioda_reset(phb, true); } diff --git a/include/npu3.h b/include/npu3.h index 0fdad4df..dda60ae1 100644 --- a/include/npu3.h +++ b/include/npu3.h @@ -20,6 +20,7 @@ #include #include #include +#include enum npu3_dev_type { NPU3_DEV_TYPE_UNKNOWN = 0, @@ -183,4 +184,9 @@ static inline int npu3_get_phb_index(unsigned int npu_index) return NPU3_PHB_INDEX_BASE + npu_index; } +static inline int npu3_get_opal_id(unsigned int chip_id, unsigned int index) +{ + return phb4_get_opal_id(chip_id, index); +} + #endif /* __NPU3_H */ diff --git a/include/phb4.h b/include/phb4.h index af2e3eda..adc19f84 100644 --- a/include/phb4.h +++ b/include/phb4.h @@ -245,10 +245,15 @@ static inline void phb4_set_err_pending(struct phb4 *p, bool pending) } #define PHB4_PER_CHIP 6 /* Max 6 PHBs per chip on p9 */ +#define PHB4_MAX_PHBS_PER_CHIP_P9 PHB4_PER_CHIP +#define PHB4_MAX_PHBS_PER_CHIP_P9P 0x10 /* extra for virt PHBs */ static inline int phb4_get_opal_id(unsigned int chip_id, unsigned int index) { - return chip_id * PHB4_PER_CHIP + index; + if (PVR_TYPE(mfspr(SPR_PVR)) == PVR_TYPE_P9) + return chip_id * PHB4_MAX_PHBS_PER_CHIP_P9 + index; + else + return chip_id * PHB4_MAX_PHBS_PER_CHIP_P9P + index; } #endif /* __PHB4_H */