From patchwork Fri Aug 9 08:29:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lokesh Vutla X-Patchwork-Id: 1144497 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="wj8n0jj7"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 464djZ30XFz9sP3 for ; Fri, 9 Aug 2019 18:30:42 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2405395AbfHIIaj (ORCPT ); Fri, 9 Aug 2019 04:30:39 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:48544 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2405818AbfHIIaj (ORCPT ); Fri, 9 Aug 2019 04:30:39 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id x798UZ1I117633; Fri, 9 Aug 2019 03:30:35 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1565339435; bh=4Xbkn6elvsTb+7O7XxccoWaDLZ3csgRAgOrOdCJJ2o4=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=wj8n0jj7s9RmTUkgCNZBrx/at6fTh7B+zpI6WmrpGqYTEsf6SqD/tfiJzbk2WDLND vHWsyo/uSonk7NmQTQqRKZUB4CXGmTjjIskkzYeOb5ElXoN7V3rqsE9aXrRz306mKN 8/EB5DxudO10hVEIM5wQMt1HbYDgo7NKLbHNfUTE= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x798UZ88117311 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 9 Aug 2019 03:30:35 -0500 Received: from DFLE105.ent.ti.com (10.64.6.26) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Fri, 9 Aug 2019 03:30:34 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Fri, 9 Aug 2019 03:30:34 -0500 Received: from uda0131933.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id x798USdf070370; Fri, 9 Aug 2019 03:30:32 -0500 From: Lokesh Vutla To: Tero Kristo , Nishanth Menon , CC: Keerthy , Rob Herring , , Device Tree Mailing List , Linux ARM Mailing List , Lokesh Vutla Subject: [PATCH 1/6] dt-bindings: gpio: davinci: Add new compatible for J721E SoCs Date: Fri, 9 Aug 2019 13:59:42 +0530 Message-ID: <20190809082947.30590-2-lokeshvutla@ti.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190809082947.30590-1-lokeshvutla@ti.com> References: <20190809082947.30590-1-lokeshvutla@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org J721e SoCs have same gpio IP as K2G davinci gpio. Add a new compatible to handle J721E SoCs. Signed-off-by: Lokesh Vutla Reviewed-by: Keerthy --- Documentation/devicetree/bindings/gpio/gpio-davinci.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/gpio/gpio-davinci.txt b/Documentation/devicetree/bindings/gpio/gpio-davinci.txt index bc6b4b62df83..cd91d61eac31 100644 --- a/Documentation/devicetree/bindings/gpio/gpio-davinci.txt +++ b/Documentation/devicetree/bindings/gpio/gpio-davinci.txt @@ -6,6 +6,7 @@ Required Properties: 66AK2E SoCs "ti,k2g-gpio", "ti,keystone-gpio": for 66AK2G "ti,am654-gpio", "ti,keystone-gpio": for TI K3 AM654 + "ti,j721e-gpio", "ti,keystone-gpio": for J721E SoCs - reg: Physical base address of the controller and the size of memory mapped registers.