| Message ID | 20190806061553.19934-2-xiaowei.bao@nxp.com |
|---|---|
| State | Superseded |
| Delegated to: | Lorenzo Pieralisi |
| Headers | show |
| Series | [PATCHv3,1/3] dt-bindings: pci: layerscape-pci: add compatible strings "fsl,ls1028a-pcie" | expand |
Hi Xiaowei, > -----Original Message----- > From: Xiaowei Bao <xiaowei.bao@nxp.com> > Sent: 2019年8月6日 14:16 > To: bhelgaas@google.com; robh+dt@kernel.org; mark.rutland@arm.com; > shawnguo@kernel.org; Leo Li <leoyang.li@nxp.com>; kishon@ti.com; > lorenzo.pieralisi@arm.com; arnd@arndb.de; gregkh@linuxfoundation.org; > M.h. Lian <minghuan.lian@nxp.com>; Mingkai Hu <mingkai.hu@nxp.com>; > Z.q. Hou <zhiqiang.hou@nxp.com>; Roy Zang <roy.zang@nxp.com>; > kstewart@linuxfoundation.org; pombredanne@nexb.com; > shawn.lin@rock-chips.com; linux-pci@vger.kernel.org; > devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; > linux-arm-kernel@lists.infradead.org; linuxppc-dev@lists.ozlabs.org > Cc: Xiaowei Bao <xiaowei.bao@nxp.com>; Z.q. Hou > <zhiqiang.hou@nxp.com> > Subject: [PATCHv3 2/3] arm64: dts: ls1028a: Add PCIe controller DT nodes > > LS1028a implements 2 PCIe 3.0 controllers. > > Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> > --- > v2: > - Fix up the legacy INTx allocate failed issue. > v3: > - no change. > > arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 52 > ++++++++++++++++++++++++++ > 1 file changed, 52 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi > b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi > index aef5b06..0b542ed 100644 > --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi > @@ -503,6 +503,58 @@ > status = "disabled"; > }; > > + pcie@3400000 { > + compatible = "fsl,ls1028a-pcie"; > + reg = <0x00 0x03400000 0x0 0x00100000 /* controller > registers */ > + 0x80 0x00000000 0x0 0x00002000>; /* configuration > space */ > + reg-names = "regs", "config"; > + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME > interrupt */ > + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; /* aer > interrupt */ > + interrupt-names = "pme", "aer"; > + #address-cells = <3>; > + #size-cells = <2>; > + device_type = "pci"; > + dma-coherent; > + num-lanes = <4>; Remove the num-lanes, it is not needed by Layerscape PCIe controllers. see: http://patchwork.ozlabs.org/project/linux-pci/list/?series=124488 > + bus-range = <0x0 0xff>; > + ranges = <0x81000000 0x0 0x00000000 0x80 0x00010000 0x0 > 0x00010000 /* downstream I/O */ > + 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 > 0x40000000>; /* non-prefetchable memory */ > + msi-parent = <&its>; > + #interrupt-cells = <1>; > + interrupt-map-mask = <0 0 0 7>; > + interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 > IRQ_TYPE_LEVEL_HIGH>, > + <0000 0 0 2 &gic 0 0 GIC_SPI 110 > IRQ_TYPE_LEVEL_HIGH>, > + <0000 0 0 3 &gic 0 0 GIC_SPI 111 > IRQ_TYPE_LEVEL_HIGH>, > + <0000 0 0 4 &gic 0 0 GIC_SPI 112 > IRQ_TYPE_LEVEL_HIGH>; > + status = "disabled"; > + }; > + > + pcie@3500000 { > + compatible = "fsl,ls1028a-pcie"; > + reg = <0x00 0x03500000 0x0 0x00100000 /* controller > registers */ > + 0x88 0x00000000 0x0 0x00002000>; /* configuration > space */ > + reg-names = "regs", "config"; > + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "pme", "aer"; > + #address-cells = <3>; > + #size-cells = <2>; > + device_type = "pci"; > + dma-coherent; > + num-lanes = <4>; Ditto > + bus-range = <0x0 0xff>; > + ranges = <0x81000000 0x0 0x00000000 0x88 0x00010000 0x0 > 0x00010000 /* downstream I/O */ > + 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 > 0x40000000>; /* non-prefetchable memory */ > + msi-parent = <&its>; > + #interrupt-cells = <1>; > + interrupt-map-mask = <0 0 0 7>; > + interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 > IRQ_TYPE_LEVEL_HIGH>, > + <0000 0 0 2 &gic 0 0 GIC_SPI 115 > IRQ_TYPE_LEVEL_HIGH>, > + <0000 0 0 3 &gic 0 0 GIC_SPI 116 > IRQ_TYPE_LEVEL_HIGH>, > + <0000 0 0 4 &gic 0 0 GIC_SPI 117 > IRQ_TYPE_LEVEL_HIGH>; > + status = "disabled"; > + }; > + > pcie@1f0000000 { /* Integrated Endpoint Root Complex */ > compatible = "pci-host-ecam-generic"; > reg = <0x01 0xf0000000 0x0 0x100000>; > -- > 2.9.5
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index aef5b06..0b542ed 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -503,6 +503,58 @@ status = "disabled"; }; + pcie@3400000 { + compatible = "fsl,ls1028a-pcie"; + reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ + 0x80 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "regs", "config"; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ + interrupt-names = "pme", "aer"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + num-lanes = <4>; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x80 0x00010000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&its>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + pcie@3500000 { + compatible = "fsl,ls1028a-pcie"; + reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ + 0x88 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "regs", "config"; + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pme", "aer"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + num-lanes = <4>; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x88 0x00010000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&its>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + pcie@1f0000000 { /* Integrated Endpoint Root Complex */ compatible = "pci-host-ecam-generic"; reg = <0x01 0xf0000000 0x0 0x100000>;