[2/2] npu3: Initialize NPU3_SNP_MISC_CFG0
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Message ID 1565037207-30968-2-git-send-email-arbab@linux.ibm.com
State Accepted
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Series
  • [1/2] npu3: Rename NPU3_SM_MISC_CFGn register macros
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Commit Message

Reza Arbab Aug. 5, 2019, 8:33 p.m. UTC
Enable powerbus snooping here, or else MMIO to any NTL/NDL registers
will cause a checkstop.

This was not an issue in Simics simulation, but discovered rather
quickly during bringup on a real Axone chip.

Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
---
 hw/npu3.c           | 7 +++++++
 include/npu3-regs.h | 4 ++++
 2 files changed, 11 insertions(+)

Comments

christophe lombard Aug. 8, 2019, 8:31 a.m. UTC | #1
On 05/08/2019 22:33, Reza Arbab wrote:
> Enable powerbus snooping here, or else MMIO to any NTL/NDL registers
> will cause a checkstop.
> 
> This was not an issue in Simics simulation, but discovered rather
> quickly during bringup on a real Axone chip.
> 
> Signed-off-by: Reza Arbab <arbab@linux.ibm.com>


Reviewed-by: Christophe Lombard <clombard@linux.vnet.ibm.com>

Patch
diff mbox series

diff --git a/hw/npu3.c b/hw/npu3.c
index ea687f43c5e7..4d396b09b806 100644
--- a/hw/npu3.c
+++ b/hw/npu3.c
@@ -309,6 +309,13 @@  static void npu3_misc_config(struct npu3 *npu)
 	val = SETFIELD(NPU3_MCP_MISC_CFG0_OCAPI_MODE, val, ~typemap);
 	npu3_write(npu, reg, val);
 
+	reg = NPU3_SNP_MISC_CFG0;
+	val = npu3_read(npu, reg);
+	val |= NPU3_SNP_MISC_CFG0_ENABLE_PBUS;
+	val = SETFIELD(NPU3_SNP_MISC_CFG0_NVLINK_MODE, val, typemap);
+	val = SETFIELD(NPU3_SNP_MISC_CFG0_OCAPI_MODE, val, ~typemap);
+	npu3_write(npu, reg, val);
+
 	reg = NPU3_CTL_MISC_CFG2;
 	val = npu3_read(npu, reg);
 	val = SETFIELD(NPU3_CTL_MISC_CFG2_NVLINK_MODE, val, typemap);
diff --git a/include/npu3-regs.h b/include/npu3-regs.h
index c0c7eab0396d..341d652899c3 100644
--- a/include/npu3-regs.h
+++ b/include/npu3-regs.h
@@ -93,6 +93,10 @@ 
 #define   NPU3_MCP_MISC_CFG0_NVLINK_MODE	PPC_BITMASK(49, 53)
 #define NPU3_MCP_MISC_CFG1			(NPU3_BLOCK_CQ_SM(0) + 0x008)
 #define NPU3_MCP_MISC_CFG2			(NPU3_BLOCK_CQ_SM(0) + 0x0f0)
+#define NPU3_SNP_MISC_CFG0			(NPU3_BLOCK_CQ_SM(0) + 0x180)
+#define   NPU3_SNP_MISC_CFG0_ENABLE_PBUS	PPC_BIT(2)
+#define   NPU3_SNP_MISC_CFG0_OCAPI_MODE		PPC_BITMASK(32, 36)
+#define   NPU3_SNP_MISC_CFG0_NVLINK_MODE	PPC_BITMASK(37, 41)
 #define NPU3_GPU_MEM_BAR(brk)			(NPU3_BLOCK_CQ_SM(0) + 0x190 + (brk) * 8)
 #define   NPU3_GPU_MEM_BAR_ENABLE		PPC_BIT(0)
 #define   NPU3_GPU_MEM_BAR_ADDR_MASK		PPC_BITMASK(1, 35)