From patchwork Sun Sep 11 13:29:58 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Blue Swirl X-Patchwork-Id: 114217 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 4407DB71E9 for ; Sun, 11 Sep 2011 23:30:43 +1000 (EST) Received: from localhost ([::1]:49258 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1R2k7G-00077p-Co for incoming@patchwork.ozlabs.org; Sun, 11 Sep 2011 09:30:34 -0400 Received: from eggs.gnu.org ([140.186.70.92]:42417) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1R2k73-0006no-0r for qemu-devel@nongnu.org; Sun, 11 Sep 2011 09:30:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1R2k70-0004ex-SI for qemu-devel@nongnu.org; Sun, 11 Sep 2011 09:30:20 -0400 Received: from mail-qy0-f173.google.com ([209.85.216.173]:40922) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1R2k70-0004et-Ny for qemu-devel@nongnu.org; Sun, 11 Sep 2011 09:30:18 -0400 Received: by qyc1 with SMTP id 1so693820qyc.4 for ; Sun, 11 Sep 2011 06:30:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:from:date:message-id:subject:to:content-type; bh=2LMZbop6ZHSt+magCUH3dgrmHnxVErT8lBeG5PTuI1U=; b=FDNesiBcVhBeT/hswY1NSMZ6yeepPv/oqFEZUvtAZZXKjbAsYEX1BNRXks+6RxTRWn H1XJNlogTfH2qAl6BI7GbpNYAwJkNW9qbVtdUep8sEFjWVVGYkJfNgfKn7w6MGLiCINz LnKENYqmr86rerUmySpIl1Y56R5KrR1dfzYn8= Received: by 10.224.70.197 with SMTP id e5mr2897327qaj.125.1315747818171; Sun, 11 Sep 2011 06:30:18 -0700 (PDT) MIME-Version: 1.0 Received: by 10.224.6.129 with HTTP; Sun, 11 Sep 2011 06:29:58 -0700 (PDT) From: Blue Swirl Date: Sun, 11 Sep 2011 13:29:58 +0000 Message-ID: To: qemu-devel X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 209.85.216.173 Subject: [Qemu-devel] [PATCH 04/15] Sparc: avoid AREG0 for raise_exception and helper_debug X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Make raise_exception() and helper_debug() take a parameter for CPUState instead of relying on global env. Move the functions to helper.c. Signed-off-by: Blue Swirl --- target-sparc/helper.c | 12 ++++++ target-sparc/helper.h | 4 +- target-sparc/op_helper.c | 100 ++++++++++++++++++++-------------------------- target-sparc/translate.c | 26 ++++++------ 4 files changed, 70 insertions(+), 72 deletions(-) tcg_temp_free(r_temp); @@ -310,7 +310,7 @@ static inline void gen_tag_tv(TCGv src1, TCGv src2) tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3); tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1); r_const = tcg_const_i32(TT_TOVF); - gen_helper_raise_exception(r_const); + gen_helper_raise_exception(cpu_env, r_const); tcg_temp_free_i32(r_const); gen_set_label(l1); } @@ -492,7 +492,7 @@ static inline void gen_sub_tv(TCGv dst, TCGv src1, TCGv src2) tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31)); tcg_gen_brcondi_tl(TCG_COND_EQ, r_temp, 0, l1); r_const = tcg_const_i32(TT_TOVF); - gen_helper_raise_exception(r_const); + gen_helper_raise_exception(cpu_env, r_const); tcg_temp_free_i32(r_const); gen_set_label(l1); tcg_temp_free(r_temp); @@ -719,7 +719,7 @@ static inline void gen_trap_ifdivzero_tl(TCGv divisor) l1 = gen_new_label(); tcg_gen_brcondi_tl(TCG_COND_NE, divisor, 0, l1); r_const = tcg_const_i32(TT_DIV_ZERO); - gen_helper_raise_exception(r_const); + gen_helper_raise_exception(cpu_env, r_const); tcg_temp_free_i32(r_const); gen_set_label(l1); } @@ -1549,7 +1549,7 @@ static inline void gen_op_fpexception_im(int fsr_flags) tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_NMASK); tcg_gen_ori_tl(cpu_fsr, cpu_fsr, fsr_flags); r_const = tcg_const_i32(TT_FP_EXCP); - gen_helper_raise_exception(r_const); + gen_helper_raise_exception(cpu_env, r_const); tcg_temp_free_i32(r_const); } @@ -1561,7 +1561,7 @@ static int gen_trap_ifnofpu(DisasContext *dc, TCGv r_cond) save_state(dc, r_cond); r_const = tcg_const_i32(TT_NFPU_INSN); - gen_helper_raise_exception(r_const); + gen_helper_raise_exception(cpu_env, r_const); tcg_temp_free_i32(r_const); dc->is_br = 1; return 1; @@ -2038,7 +2038,7 @@ static void disas_sparc_insn(DisasContext * dc) gen_helper_shutdown(); } else { - gen_helper_raise_exception(cpu_tmp32); + gen_helper_raise_exception(cpu_env, cpu_tmp32); } } else if (cond != 0) { TCGv r_cond = tcg_temp_new(); @@ -2068,7 +2068,7 @@ static void disas_sparc_insn(DisasContext * dc) tcg_gen_andi_tl(cpu_dst, cpu_dst, V8_TRAP_MASK); tcg_gen_addi_tl(cpu_dst, cpu_dst, TT_TRAP); tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst); - gen_helper_raise_exception(cpu_tmp32); + gen_helper_raise_exception(cpu_env, cpu_tmp32); gen_set_label(l1); tcg_temp_free(r_cond); @@ -4931,7 +4931,7 @@ static void disas_sparc_insn(DisasContext * dc) save_state(dc, cpu_cond); r_const = tcg_const_i32(TT_ILL_INSN); - gen_helper_raise_exception(r_const); + gen_helper_raise_exception(cpu_env, r_const); tcg_temp_free_i32(r_const); dc->is_br = 1; } @@ -4942,7 +4942,7 @@ static void disas_sparc_insn(DisasContext * dc) save_state(dc, cpu_cond); r_const = tcg_const_i32(TT_UNIMP_FLUSH); - gen_helper_raise_exception(r_const); + gen_helper_raise_exception(cpu_env, r_const); tcg_temp_free_i32(r_const); dc->is_br = 1; } @@ -4954,7 +4954,7 @@ static void disas_sparc_insn(DisasContext * dc) save_state(dc, cpu_cond); r_const = tcg_const_i32(TT_PRIV_INSN); - gen_helper_raise_exception(r_const); + gen_helper_raise_exception(cpu_env, r_const); tcg_temp_free_i32(r_const); dc->is_br = 1; } @@ -4979,7 +4979,7 @@ static void disas_sparc_insn(DisasContext * dc) save_state(dc, cpu_cond); r_const = tcg_const_i32(TT_NCP_INSN); - gen_helper_raise_exception(r_const); + gen_helper_raise_exception(cpu_env, r_const); tcg_temp_free(r_const); dc->is_br = 1; } @@ -5036,7 +5036,7 @@ static inline void gen_intermediate_code_internal(TranslationBlock * tb, if (bp->pc == dc->pc) { if (dc->pc != pc_start) save_state(dc, cpu_cond); - gen_helper_debug(); + gen_helper_debug(cpu_env); tcg_gen_exit_tb(0); dc->is_br = 1; goto exit_gen_loop; diff --git a/target-sparc/helper.c b/target-sparc/helper.c index e9182ac..7a25605 100644 --- a/target-sparc/helper.c +++ b/target-sparc/helper.c @@ -871,6 +871,18 @@ target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) #endif /* misc op helpers */ +void helper_raise_exception(CPUState *env, int tt) +{ + env->exception_index = tt; + cpu_loop_exit(env); +} + +void helper_debug(CPUState *env) +{ + env->exception_index = EXCP_DEBUG; + cpu_loop_exit(env); +} + void helper_shutdown(void) { #if !defined(CONFIG_USER_ONLY) diff --git a/target-sparc/helper.h b/target-sparc/helper.h index 2d36af3..a452666 100644 --- a/target-sparc/helper.h +++ b/target-sparc/helper.h @@ -32,7 +32,7 @@ DEF_HELPER_1(tick_get_count, i64, ptr) DEF_HELPER_2(tick_set_limit, void, ptr, i64) #endif DEF_HELPER_2(check_align, void, tl, i32) -DEF_HELPER_0(debug, void) +DEF_HELPER_1(debug, void, env) DEF_HELPER_0(save, void) DEF_HELPER_0(restore, void) DEF_HELPER_2(udiv, tl, tl, tl) @@ -83,7 +83,7 @@ DEF_HELPER_0(fcmpeq_fcc1, void) DEF_HELPER_0(fcmpeq_fcc2, void) DEF_HELPER_0(fcmpeq_fcc3, void) #endif -DEF_HELPER_1(raise_exception, void, int) +DEF_HELPER_2(raise_exception, void, env, int) DEF_HELPER_0(shutdown, void) #define F_HELPER_0_0(name) DEF_HELPER_0(f ## name, void) #define F_HELPER_DQ_0_0(name) \ diff --git a/target-sparc/op_helper.c b/target-sparc/op_helper.c index dbdccea..6a333c1 100644 --- a/target-sparc/op_helper.c +++ b/target-sparc/op_helper.c @@ -321,17 +321,6 @@ static inline target_ulong asi_address_mask(CPUState *env1, } } -static void raise_exception(int tt) -{ - env->exception_index = tt; - cpu_loop_exit(env); -} - -void HELPER(raise_exception)(int tt) -{ - raise_exception(tt); -} - void helper_check_align(target_ulong addr, uint32_t align) { if (addr & align) { @@ -339,7 +328,7 @@ void helper_check_align(target_ulong addr, uint32_t align) printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx "\n", addr, env->pc); #endif - raise_exception(TT_UNALIGNED); + helper_raise_exception(env, TT_UNALIGNED); } } @@ -853,7 +842,7 @@ void helper_check_ieee_exceptions(void) if ((env->fsr & FSR_CEXC_MASK) & ((env->fsr & FSR_TEM_MASK) >> 23)) { /* Unmasked exception, generate a trap */ env->fsr |= FSR_FTT_IEEE_EXCP; - raise_exception(TT_FP_EXCP); + helper_raise_exception(env, TT_FP_EXCP); } else { /* Accumulate exceptions */ env->fsr |= (env->fsr & FSR_CEXC_MASK) << 5; @@ -907,14 +896,14 @@ void helper_fsqrtq(void) (env->fsr & FSR_NVM)) { \ env->fsr |= FSR_NVC; \ env->fsr |= FSR_FTT_IEEE_EXCP; \ - raise_exception(TT_FP_EXCP); \ + helper_raise_exception(env, TT_FP_EXCP); \ } \ switch (glue(size, _compare) (reg1, reg2, &env->fp_status)) { \ case float_relation_unordered: \ if ((env->fsr & FSR_NVM)) { \ env->fsr |= FSR_NVC; \ env->fsr |= FSR_FTT_IEEE_EXCP; \ - raise_exception(TT_FP_EXCP); \ + helper_raise_exception(env, TT_FP_EXCP); \ } else { \ env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \ env->fsr |= (FSR_FCC1 | FSR_FCC0) << FS; \ @@ -943,14 +932,14 @@ void helper_fsqrtq(void) (env->fsr & FSR_NVM)) { \ env->fsr |= FSR_NVC; \ env->fsr |= FSR_FTT_IEEE_EXCP; \ - raise_exception(TT_FP_EXCP); \ + helper_raise_exception(env, TT_FP_EXCP); \ } \ switch (glue(size, _compare) (src1, src2, &env->fp_status)) { \ case float_relation_unordered: \ if ((env->fsr & FSR_NVM)) { \ env->fsr |= FSR_NVC; \ env->fsr |= FSR_FTT_IEEE_EXCP; \ - raise_exception(TT_FP_EXCP); \ + helper_raise_exception(env, TT_FP_EXCP); \ } else { \ env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \ env->fsr |= (FSR_FCC1 | FSR_FCC0) << FS; \ @@ -2377,7 +2366,7 @@ uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign) #endif if (asi < 0x80) - raise_exception(TT_PRIV_ACT); + helper_raise_exception(env, TT_PRIV_ACT); helper_check_align(addr, size - 1); addr = asi_address_mask(env, asi, addr); @@ -2480,7 +2469,7 @@ void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size) dump_asi("write", addr, asi, size, val); #endif if (asi < 0x80) - raise_exception(TT_PRIV_ACT); + helper_raise_exception(env, TT_PRIV_ACT); helper_check_align(addr, size - 1); addr = asi_address_mask(env, asi, addr); @@ -2557,7 +2546,7 @@ uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign) || (cpu_has_hypervisor(env) && asi >= 0x30 && asi < 0x80 && !(env->hpstate & HS_PRIV))) - raise_exception(TT_PRIV_ACT); + helper_raise_exception(env, TT_PRIV_ACT); helper_check_align(addr, size - 1); addr = asi_address_mask(env, asi, addr); @@ -2578,7 +2567,7 @@ uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign) dump_asi("read ", last_addr, asi, size, ret); #endif /* env->exception_index is set in get_physical_address_data(). */ - raise_exception(env->exception_index); + helper_raise_exception(env, env->exception_index); } /* convert nonfaulting load ASIs to normal load ASIs */ @@ -2711,7 +2700,7 @@ uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign) case 0x24: // Nucleus quad LDD 128 bit atomic case 0x2c: // Nucleus quad LDD 128 bit atomic LE // Only ldda allowed - raise_exception(TT_ILL_INSN); + helper_raise_exception(env, TT_ILL_INSN); return 0; case 0x04: // Nucleus case 0x0c: // Nucleus Little Endian (LE) @@ -2914,7 +2903,7 @@ void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size) || (cpu_has_hypervisor(env) && asi >= 0x30 && asi < 0x80 && !(env->hpstate & HS_PRIV))) - raise_exception(TT_PRIV_ACT); + helper_raise_exception(env, TT_PRIV_ACT); helper_check_align(addr, size - 1); addr = asi_address_mask(env, asi, addr); @@ -3071,7 +3060,7 @@ void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size) case 0x24: // Nucleus quad LDD 128 bit atomic case 0x2c: // Nucleus quad LDD 128 bit atomic LE // Only ldda allowed - raise_exception(TT_ILL_INSN); + helper_raise_exception(env, TT_ILL_INSN); return; case 0x04: // Nucleus case 0x0c: // Nucleus Little Endian (LE) @@ -3291,7 +3280,7 @@ void helper_ldda_asi(target_ulong addr, int asi, int rd) || (cpu_has_hypervisor(env) && asi >= 0x30 && asi < 0x80 && !(env->hpstate & HS_PRIV))) - raise_exception(TT_PRIV_ACT); + helper_raise_exception(env, TT_PRIV_ACT); addr = asi_address_mask(env, asi, addr); @@ -3350,7 +3339,7 @@ void helper_ldf_asi(target_ulong addr, int asi, int size, int rd) case 0xf8: /* UA2007/JPS1 Block load primary LE */ case 0xf9: /* UA2007/JPS1 Block load secondary LE */ if (rd & 7) { - raise_exception(TT_ILL_INSN); + helper_raise_exception(env, TT_ILL_INSN); return; } helper_check_align(addr, 0x3f); @@ -3370,7 +3359,7 @@ void helper_ldf_asi(target_ulong addr, int asi, int size, int rd) case 0x78: /* JPS1 Block load primary LE, user privilege */ case 0x79: /* JPS1 Block load secondary LE, user privilege */ if (rd & 7) { - raise_exception(TT_ILL_INSN); + helper_raise_exception(env, TT_ILL_INSN); return; } helper_check_align(addr, 0x3f); @@ -3423,7 +3412,7 @@ void helper_stf_asi(target_ulong addr, int asi, int size, int rd) case 0xf8: /* UA2007/JPS1 Block store primary LE */ case 0xf9: /* UA2007/JPS1 Block store secondary LE */ if (rd & 7) { - raise_exception(TT_ILL_INSN); + helper_raise_exception(env, TT_ILL_INSN); return; } helper_check_align(addr, 0x3f); @@ -3443,7 +3432,7 @@ void helper_stf_asi(target_ulong addr, int asi, int size, int rd) case 0x78: /* JPS1 Block load primary LE, user privilege */ case 0x79: /* JPS1 Block load secondary LE, user privilege */ if (rd & 7) { - raise_exception(TT_ILL_INSN); + helper_raise_exception(env, TT_ILL_INSN); return; } helper_check_align(addr, 0x3f); @@ -3510,12 +3499,12 @@ void helper_rett(void) unsigned int cwp; if (env->psret == 1) - raise_exception(TT_ILL_INSN); + helper_raise_exception(env, TT_ILL_INSN); env->psret = 1; cwp = cwp_inc(env->cwp + 1) ; if (env->wim & (1 << cwp)) { - raise_exception(TT_WIN_UNF); + helper_raise_exception(env, TT_WIN_UNF); } set_cwp(cwp); env->psrs = env->psrps; @@ -3532,7 +3521,7 @@ static target_ulong helper_udiv_common(target_ulong a, target_ulong b, int cc) x1 = (b & 0xffffffff); if (x1 == 0) { - raise_exception(TT_DIV_ZERO); + helper_raise_exception(env, TT_DIV_ZERO); } x0 = x0 / x1; @@ -3569,7 +3558,7 @@ static target_ulong helper_sdiv_common(target_ulong a, target_ulong b, int cc) x1 = (b & 0xffffffff); if (x1 == 0) { - raise_exception(TT_DIV_ZERO); + helper_raise_exception(env, TT_DIV_ZERO); } x0 = x0 / x1; @@ -3754,12 +3743,6 @@ void helper_ldxfsr(uint64_t new_fsr) } #endif -void helper_debug(void) -{ - env->exception_index = EXCP_DEBUG; - cpu_loop_exit(env); -} - #ifndef TARGET_SPARC64 /* XXX: use another pointer for %iN registers to avoid slow wrapping handling ? */ @@ -3769,7 +3752,7 @@ void helper_save(void) cwp = cwp_dec(env->cwp - 1); if (env->wim & (1 << cwp)) { - raise_exception(TT_WIN_OVF); + helper_raise_exception(env, TT_WIN_OVF); } set_cwp(cwp); } @@ -3780,7 +3763,7 @@ void helper_restore(void) cwp = cwp_inc(env->cwp + 1); if (env->wim & (1 << cwp)) { - raise_exception(TT_WIN_UNF); + helper_raise_exception(env, TT_WIN_UNF); } set_cwp(cwp); } @@ -3788,7 +3771,7 @@ void helper_restore(void) void helper_wrpsr(target_ulong new_psr) { if ((new_psr & PSR_CWP) >= env->nwindows) { - raise_exception(TT_ILL_INSN); + helper_raise_exception(env, TT_ILL_INSN); } else { cpu_put_psr(env, new_psr); } @@ -3808,13 +3791,14 @@ void helper_save(void) cwp = cwp_dec(env->cwp - 1); if (env->cansave == 0) { - raise_exception(TT_SPILL | (env->otherwin != 0 ? - (TT_WOTHER | ((env->wstate & 0x38) >> 1)): - ((env->wstate & 0x7) << 2))); + helper_raise_exception(env, TT_SPILL | (env->otherwin != 0 ? + (TT_WOTHER | + ((env->wstate & 0x38) >> 1)) : + ((env->wstate & 0x7) << 2))); } else { if (env->cleanwin - env->canrestore == 0) { // XXX Clean windows without trap - raise_exception(TT_CLRWIN); + helper_raise_exception(env, TT_CLRWIN); } else { env->cansave--; env->canrestore++; @@ -3829,9 +3813,10 @@ void helper_restore(void) cwp = cwp_inc(env->cwp + 1); if (env->canrestore == 0) { - raise_exception(TT_FILL | (env->otherwin != 0 ? - (TT_WOTHER | ((env->wstate & 0x38) >> 1)): - ((env->wstate & 0x7) << 2))); + helper_raise_exception(env, TT_FILL | (env->otherwin != 0 ? + (TT_WOTHER | + ((env->wstate & 0x38) >> 1)) : + ((env->wstate & 0x7) << 2))); } else { env->cansave++; env->canrestore--; @@ -3842,9 +3827,10 @@ void helper_restore(void) void helper_flushw(void) { if (env->cansave != env->nwindows - 2) { - raise_exception(TT_SPILL | (env->otherwin != 0 ? - (TT_WOTHER | ((env->wstate & 0x38) >> 1)): - ((env->wstate & 0x7) << 2))); + helper_raise_exception(env, TT_SPILL | (env->otherwin != 0 ? + (TT_WOTHER | + ((env->wstate & 0x38) >> 1)) : + ((env->wstate & 0x7) << 2))); } } @@ -4196,7 +4182,7 @@ static void do_unaligned_access(target_ulong addr, int is_write, int is_user, "\n", addr, env->pc); #endif cpu_restore_state2(retaddr); - raise_exception(TT_UNALIGNED); + helper_raise_exception(env, TT_UNALIGNED); } /* try to fill the TLB and return an exception if error. If retaddr is @@ -4267,9 +4253,9 @@ static void do_unassigned_access(target_phys_addr_t addr, int is_write, if ((env->mmuregs[0] & MMU_E) && !(env->mmuregs[0] & MMU_NF)) { if (is_exec) - raise_exception(TT_CODE_ACCESS); + helper_raise_exception(env, TT_CODE_ACCESS); else - raise_exception(TT_DATA_ACCESS); + helper_raise_exception(env, TT_DATA_ACCESS); } /* flush neverland mappings created during no-fault mode, @@ -4294,9 +4280,9 @@ static void do_unassigned_access(target_phys_addr_t addr, int is_write, #endif if (is_exec) - raise_exception(TT_CODE_ACCESS); + helper_raise_exception(env, TT_CODE_ACCESS); else - raise_exception(TT_DATA_ACCESS); + helper_raise_exception(env, TT_DATA_ACCESS); } #endif diff --git a/target-sparc/translate.c b/target-sparc/translate.c index dee67b3..9dd6b34 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -294,7 +294,7 @@ static inline void gen_add_tv(TCGv dst, TCGv src1, TCGv src2) tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31)); tcg_gen_brcondi_tl(TCG_COND_EQ, r_temp, 0, l1); r_const = tcg_const_i32(TT_TOVF); - gen_helper_raise_exception(r_const); + gen_helper_raise_exception(cpu_env, r_const); tcg_temp_free_i32(r_const); gen_set_label(l1);