From patchwork Sat Sep 10 10:29:43 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: arm: mx28: check for gated clocks when setting saif divider Date: Sat, 10 Sep 2011 00:29:43 -0000 From: Wolfram Sang X-Patchwork-Id: 114156 Message-Id: <1315650583-4793-1-git-send-email-w.sang@pengutronix.de> To: linux-arm-kernel@lists.infradead.org Cc: Sascha Hauer , Dong Aisheng-B29396 , Wolfram Sang , Shawn Guo Like with all other clocks, the divider for the SAIF devices should not be altered when the clock is gated. Bail out when this is the case like the other clocks do. Signed-off-by: Wolfram Sang Cc: Sascha Hauer Cc: Shawn Guo Cc: Dong Aisheng-B29396 --- Aisheng: I think this is the correct solution for clock-mx28.c. If setting the rate of the saif clocks hit the error path, it should be fixed in the driver? arch/arm/mach-mxs/clock-mx28.c | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-mxs/clock-mx28.c b/arch/arm/mach-mxs/clock-mx28.c index 63d6117..c9482b5 100644 --- a/arch/arm/mach-mxs/clock-mx28.c +++ b/arch/arm/mach-mxs/clock-mx28.c @@ -457,6 +457,10 @@ static int name##_set_rate(struct clk *clk, unsigned long rate) \ reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs); \ reg &= ~BM_CLKCTRL_##rs##_DIV; \ reg |= div << BP_CLKCTRL_##rs##_DIV; \ + if (reg & (1 << clk->enable_shift)) { \ + pr_err("%s: clock is gated\n", __func__); \ + return -EINVAL; \ + } \ __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs); \ \ for (i = 10000; i; i--) \