| Message ID | 1564607463-28802-2-git-send-email-skomatineni@nvidia.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | SC7 entry and exit support for Tegra210 | expand |
On Wed, Jul 31, 2019 at 11:11 PM Sowjanya Komatineni <skomatineni@nvidia.com> wrote: > This patch adds support for Tegra pinctrl driver suspend and resume. > > During suspend, context of all pinctrl registers are stored and > on resume they are all restored to have all the pinmux and pad > configuration for normal operation. > > Acked-by: Thierry Reding <treding@nvidia.com> > Reviewed-by: Dmitry Osipenko <digetx@gmail.com> > Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Patch applied to the pinctrl tree. This patch seems finished. Also if the rest don't get merged for v5.4 then at least this is so your patch stack gets more shallow. I hope it's fine to merge this separately, else tell me and I'll pull it out. Yours, Linus Walleij
01.08.2019 0:10, Sowjanya Komatineni пишет: > This patch adds support for Tegra pinctrl driver suspend and resume. > > During suspend, context of all pinctrl registers are stored and > on resume they are all restored to have all the pinmux and pad > configuration for normal operation. > > Acked-by: Thierry Reding <treding@nvidia.com> > Reviewed-by: Dmitry Osipenko <digetx@gmail.com> > Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> > --- > drivers/pinctrl/tegra/pinctrl-tegra.c | 59 +++++++++++++++++++++++++++++++++++ > drivers/pinctrl/tegra/pinctrl-tegra.h | 3 ++ > 2 files changed, 62 insertions(+) > > diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c > index 186ef98e7b2b..e3a237534281 100644 > --- a/drivers/pinctrl/tegra/pinctrl-tegra.c > +++ b/drivers/pinctrl/tegra/pinctrl-tegra.c > @@ -631,6 +631,58 @@ static void tegra_pinctrl_clear_parked_bits(struct tegra_pmx *pmx) > } > } > > +static size_t tegra_pinctrl_get_bank_size(struct device *dev, > + unsigned int bank_id) > +{ > + struct platform_device *pdev = to_platform_device(dev); > + struct resource *res; > + > + res = platform_get_resource(pdev, IORESOURCE_MEM, bank_id); > + > + return resource_size(res) / 4; > +} > + > +static int tegra_pinctrl_suspend(struct device *dev) > +{ > + struct tegra_pmx *pmx = dev_get_drvdata(dev); > + u32 *backup_regs = pmx->backup_regs; > + u32 *regs; > + size_t bank_size; > + unsigned int i, k; > + > + for (i = 0; i < pmx->nbanks; i++) { > + bank_size = tegra_pinctrl_get_bank_size(dev, i); > + regs = pmx->regs[i]; > + for (k = 0; k < bank_size; k++) > + *backup_regs++ = readl_relaxed(regs++); > + } > + > + return pinctrl_force_sleep(pmx->pctl); > +} > + > +static int tegra_pinctrl_resume(struct device *dev) > +{ > + struct tegra_pmx *pmx = dev_get_drvdata(dev); > + u32 *backup_regs = pmx->backup_regs; > + u32 *regs; > + size_t bank_size; > + unsigned int i, k; > + > + for (i = 0; i < pmx->nbanks; i++) { > + bank_size = tegra_pinctrl_get_bank_size(dev, i); > + regs = pmx->regs[i]; > + for (k = 0; k < bank_size; k++) > + writel_relaxed(*backup_regs++, regs++); > + } I'm now curious whether any kind of barrier is needed after the writings. The pmx_writel() doesn't insert a barrier after the write and seems it just misuses writel, which actually should be writel_relaxed() + barrier, IIUC. It's also not obvious whether PINCTRL HW has any kind of write-FIFO and thus maybe read-back + rmb() is needed in order ensure that writes are actually completed. The last thing which is not obvious is when the new configuration actually takes into effect, does it happen immediately or maybe some delay is needed? [snip]
On 8/5/19 3:50 AM, Dmitry Osipenko wrote: > 01.08.2019 0:10, Sowjanya Komatineni пишет: >> This patch adds support for Tegra pinctrl driver suspend and resume. >> >> During suspend, context of all pinctrl registers are stored and >> on resume they are all restored to have all the pinmux and pad >> configuration for normal operation. >> >> Acked-by: Thierry Reding <treding@nvidia.com> >> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> >> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> >> --- >> drivers/pinctrl/tegra/pinctrl-tegra.c | 59 +++++++++++++++++++++++++++++++++++ >> drivers/pinctrl/tegra/pinctrl-tegra.h | 3 ++ >> 2 files changed, 62 insertions(+) >> >> diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c >> index 186ef98e7b2b..e3a237534281 100644 >> --- a/drivers/pinctrl/tegra/pinctrl-tegra.c >> +++ b/drivers/pinctrl/tegra/pinctrl-tegra.c >> @@ -631,6 +631,58 @@ static void tegra_pinctrl_clear_parked_bits(struct tegra_pmx *pmx) >> } >> } >> >> +static size_t tegra_pinctrl_get_bank_size(struct device *dev, >> + unsigned int bank_id) >> +{ >> + struct platform_device *pdev = to_platform_device(dev); >> + struct resource *res; >> + >> + res = platform_get_resource(pdev, IORESOURCE_MEM, bank_id); >> + >> + return resource_size(res) / 4; >> +} >> + >> +static int tegra_pinctrl_suspend(struct device *dev) >> +{ >> + struct tegra_pmx *pmx = dev_get_drvdata(dev); >> + u32 *backup_regs = pmx->backup_regs; >> + u32 *regs; >> + size_t bank_size; >> + unsigned int i, k; >> + >> + for (i = 0; i < pmx->nbanks; i++) { >> + bank_size = tegra_pinctrl_get_bank_size(dev, i); >> + regs = pmx->regs[i]; >> + for (k = 0; k < bank_size; k++) >> + *backup_regs++ = readl_relaxed(regs++); >> + } >> + >> + return pinctrl_force_sleep(pmx->pctl); >> +} >> + >> +static int tegra_pinctrl_resume(struct device *dev) >> +{ >> + struct tegra_pmx *pmx = dev_get_drvdata(dev); >> + u32 *backup_regs = pmx->backup_regs; >> + u32 *regs; >> + size_t bank_size; >> + unsigned int i, k; >> + >> + for (i = 0; i < pmx->nbanks; i++) { >> + bank_size = tegra_pinctrl_get_bank_size(dev, i); >> + regs = pmx->regs[i]; >> + for (k = 0; k < bank_size; k++) >> + writel_relaxed(*backup_regs++, regs++); >> + } > I'm now curious whether any kind of barrier is needed after the > writings. The pmx_writel() doesn't insert a barrier after the write and > seems it just misuses writel, which actually should be writel_relaxed() > + barrier, IIUC. pmx_writel uses writel and it has wmb before raw_write which complete all writes initiated prior to this. By misusing writel, you mean to have barrier after register write? > It's also not obvious whether PINCTRL HW has any kind of write-FIFO and > thus maybe read-back + rmb() is needed in order ensure that writes are > actually completed. I believe adding write barrier wmb after writel_relaxed should be good rather than doing readback + rmb > > The last thing which is not obvious is when the new configuration > actually takes into effect, does it happen immediately or maybe some > delay is needed? > > [snip] Based on internal design there is no internal delay and it all depends on APB rate that it takes to write to register. Pinmux value change to reflect internally might take couple of clock cycles which is much faster than SW can read.
05.08.2019 21:06, Sowjanya Komatineni пишет: > > On 8/5/19 3:50 AM, Dmitry Osipenko wrote: >> 01.08.2019 0:10, Sowjanya Komatineni пишет: >>> This patch adds support for Tegra pinctrl driver suspend and resume. >>> >>> During suspend, context of all pinctrl registers are stored and >>> on resume they are all restored to have all the pinmux and pad >>> configuration for normal operation. >>> >>> Acked-by: Thierry Reding <treding@nvidia.com> >>> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> >>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> >>> --- >>> drivers/pinctrl/tegra/pinctrl-tegra.c | 59 >>> +++++++++++++++++++++++++++++++++++ >>> drivers/pinctrl/tegra/pinctrl-tegra.h | 3 ++ >>> 2 files changed, 62 insertions(+) >>> >>> diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c >>> b/drivers/pinctrl/tegra/pinctrl-tegra.c >>> index 186ef98e7b2b..e3a237534281 100644 >>> --- a/drivers/pinctrl/tegra/pinctrl-tegra.c >>> +++ b/drivers/pinctrl/tegra/pinctrl-tegra.c >>> @@ -631,6 +631,58 @@ static void >>> tegra_pinctrl_clear_parked_bits(struct tegra_pmx *pmx) >>> } >>> } >>> +static size_t tegra_pinctrl_get_bank_size(struct device *dev, >>> + unsigned int bank_id) >>> +{ >>> + struct platform_device *pdev = to_platform_device(dev); >>> + struct resource *res; >>> + >>> + res = platform_get_resource(pdev, IORESOURCE_MEM, bank_id); >>> + >>> + return resource_size(res) / 4; >>> +} >>> + >>> +static int tegra_pinctrl_suspend(struct device *dev) >>> +{ >>> + struct tegra_pmx *pmx = dev_get_drvdata(dev); >>> + u32 *backup_regs = pmx->backup_regs; >>> + u32 *regs; >>> + size_t bank_size; >>> + unsigned int i, k; >>> + >>> + for (i = 0; i < pmx->nbanks; i++) { >>> + bank_size = tegra_pinctrl_get_bank_size(dev, i); >>> + regs = pmx->regs[i]; >>> + for (k = 0; k < bank_size; k++) >>> + *backup_regs++ = readl_relaxed(regs++); >>> + } >>> + >>> + return pinctrl_force_sleep(pmx->pctl); >>> +} >>> + >>> +static int tegra_pinctrl_resume(struct device *dev) >>> +{ >>> + struct tegra_pmx *pmx = dev_get_drvdata(dev); >>> + u32 *backup_regs = pmx->backup_regs; >>> + u32 *regs; >>> + size_t bank_size; >>> + unsigned int i, k; >>> + >>> + for (i = 0; i < pmx->nbanks; i++) { >>> + bank_size = tegra_pinctrl_get_bank_size(dev, i); >>> + regs = pmx->regs[i]; >>> + for (k = 0; k < bank_size; k++) >>> + writel_relaxed(*backup_regs++, regs++); >>> + } >> I'm now curious whether any kind of barrier is needed after the >> writings. The pmx_writel() doesn't insert a barrier after the write and >> seems it just misuses writel, which actually should be writel_relaxed() >> + barrier, IIUC. > > pmx_writel uses writel and it has wmb before raw_write which complete > all writes initiated prior to this. > > By misusing writel, you mean to have barrier after register write? Yes, at least to me it doesn't make much sense for this driver to stall before the write. It's the pinctrl user which should be taking care about everything to be ready before making a change to the pinctrl's configuration. >> It's also not obvious whether PINCTRL HW has any kind of write-FIFO and >> thus maybe read-back + rmb() is needed in order ensure that writes are >> actually completed. > I believe adding write barrier wmb after writel_relaxed should be good > rather than doing readback + rmb >> >> The last thing which is not obvious is when the new configuration >> actually takes into effect, does it happen immediately or maybe some >> delay is needed? >> >> [snip] > > Based on internal design there is no internal delay and it all depends > on APB rate that it takes to write to register. > > Pinmux value change to reflect internally might take couple of clock > cycles which is much faster than SW can read. Still not quite obvious if it's possible to have a case where some hardware is touched before necessary pinctrl change is fully completed and then to get into trouble because of it.
On 8/5/19 2:20 AM, Linus Walleij wrote: > On Wed, Jul 31, 2019 at 11:11 PM Sowjanya Komatineni > <skomatineni@nvidia.com> wrote: > >> This patch adds support for Tegra pinctrl driver suspend and resume. >> >> During suspend, context of all pinctrl registers are stored and >> on resume they are all restored to have all the pinmux and pad >> configuration for normal operation. >> >> Acked-by: Thierry Reding <treding@nvidia.com> >> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> >> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> > Patch applied to the pinctrl tree. > > This patch seems finished. > > Also if the rest don't get merged for v5.4 then at least this is so > your patch stack gets more shallow. > > I hope it's fine to merge this separately, else tell me and I'll > pull it out. > > Yours, > Linus Walleij Yes, this patch can be merged separately. But, there's latest feedback from Dmitry to add barrier after writes to make sure pinmux register writes happen. So will update this patch to add barrier in v8. So, need to wait for v8. Thanks Sowjanya
On 8/6/19 10:59 AM, Dmitry Osipenko wrote: > 05.08.2019 21:06, Sowjanya Komatineni пишет: >> On 8/5/19 3:50 AM, Dmitry Osipenko wrote: >>> 01.08.2019 0:10, Sowjanya Komatineni пишет: >>>> This patch adds support for Tegra pinctrl driver suspend and resume. >>>> >>>> During suspend, context of all pinctrl registers are stored and >>>> on resume they are all restored to have all the pinmux and pad >>>> configuration for normal operation. >>>> >>>> Acked-by: Thierry Reding <treding@nvidia.com> >>>> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> >>>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> >>>> --- >>>> drivers/pinctrl/tegra/pinctrl-tegra.c | 59 >>>> +++++++++++++++++++++++++++++++++++ >>>> drivers/pinctrl/tegra/pinctrl-tegra.h | 3 ++ >>>> 2 files changed, 62 insertions(+) >>>> >>>> diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c >>>> b/drivers/pinctrl/tegra/pinctrl-tegra.c >>>> index 186ef98e7b2b..e3a237534281 100644 >>>> --- a/drivers/pinctrl/tegra/pinctrl-tegra.c >>>> +++ b/drivers/pinctrl/tegra/pinctrl-tegra.c >>>> @@ -631,6 +631,58 @@ static void >>>> tegra_pinctrl_clear_parked_bits(struct tegra_pmx *pmx) >>>> } >>>> } >>>> +static size_t tegra_pinctrl_get_bank_size(struct device *dev, >>>> + unsigned int bank_id) >>>> +{ >>>> + struct platform_device *pdev = to_platform_device(dev); >>>> + struct resource *res; >>>> + >>>> + res = platform_get_resource(pdev, IORESOURCE_MEM, bank_id); >>>> + >>>> + return resource_size(res) / 4; >>>> +} >>>> + >>>> +static int tegra_pinctrl_suspend(struct device *dev) >>>> +{ >>>> + struct tegra_pmx *pmx = dev_get_drvdata(dev); >>>> + u32 *backup_regs = pmx->backup_regs; >>>> + u32 *regs; >>>> + size_t bank_size; >>>> + unsigned int i, k; >>>> + >>>> + for (i = 0; i < pmx->nbanks; i++) { >>>> + bank_size = tegra_pinctrl_get_bank_size(dev, i); >>>> + regs = pmx->regs[i]; >>>> + for (k = 0; k < bank_size; k++) >>>> + *backup_regs++ = readl_relaxed(regs++); >>>> + } >>>> + >>>> + return pinctrl_force_sleep(pmx->pctl); >>>> +} >>>> + >>>> +static int tegra_pinctrl_resume(struct device *dev) >>>> +{ >>>> + struct tegra_pmx *pmx = dev_get_drvdata(dev); >>>> + u32 *backup_regs = pmx->backup_regs; >>>> + u32 *regs; >>>> + size_t bank_size; >>>> + unsigned int i, k; >>>> + >>>> + for (i = 0; i < pmx->nbanks; i++) { >>>> + bank_size = tegra_pinctrl_get_bank_size(dev, i); >>>> + regs = pmx->regs[i]; >>>> + for (k = 0; k < bank_size; k++) >>>> + writel_relaxed(*backup_regs++, regs++); >>>> + } >>> I'm now curious whether any kind of barrier is needed after the >>> writings. The pmx_writel() doesn't insert a barrier after the write and >>> seems it just misuses writel, which actually should be writel_relaxed() >>> + barrier, IIUC. >> pmx_writel uses writel and it has wmb before raw_write which complete >> all writes initiated prior to this. >> >> By misusing writel, you mean to have barrier after register write? > Yes, at least to me it doesn't make much sense for this driver to stall > before the write. It's the pinctrl user which should be taking care > about everything to be ready before making a change to the pinctrl's > configuration. > >>> It's also not obvious whether PINCTRL HW has any kind of write-FIFO and >>> thus maybe read-back + rmb() is needed in order ensure that writes are >>> actually completed. >> I believe adding write barrier wmb after writel_relaxed should be good >> rather than doing readback + rmb >>> The last thing which is not obvious is when the new configuration >>> actually takes into effect, does it happen immediately or maybe some >>> delay is needed? >>> >>> [snip] >> Based on internal design there is no internal delay and it all depends >> on APB rate that it takes to write to register. >> >> Pinmux value change to reflect internally might take couple of clock >> cycles which is much faster than SW can read. > Still not quite obvious if it's possible to have a case where some > hardware is touched before necessary pinctrl change is fully completed > and then to get into trouble because of it. To be safer, will add write barrier after all writes in resume and also will have separate patch for pmx_writel fix to use writel_relaxed followed by write barrier. Thanks Sowjanya
On 8/6/19 2:51 PM, Sowjanya Komatineni wrote: > > On 8/5/19 2:20 AM, Linus Walleij wrote: >> On Wed, Jul 31, 2019 at 11:11 PM Sowjanya Komatineni >> <skomatineni@nvidia.com> wrote: >> >>> This patch adds support for Tegra pinctrl driver suspend and resume. >>> >>> During suspend, context of all pinctrl registers are stored and >>> on resume they are all restored to have all the pinmux and pad >>> configuration for normal operation. >>> >>> Acked-by: Thierry Reding <treding@nvidia.com> >>> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> >>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> >> Patch applied to the pinctrl tree. >> >> This patch seems finished. >> >> Also if the rest don't get merged for v5.4 then at least this is so >> your patch stack gets more shallow. >> >> I hope it's fine to merge this separately, else tell me and I'll >> pull it out. >> >> Yours, >> Linus Walleij > > Yes, this patch can be merged separately. But, there's latest feedback > from Dmitry to add barrier after writes to make sure pinmux register > writes happen. > > So will update this patch to add barrier in v8. So, need to wait for v8. > > Thanks > > Sowjanya > I see it merged. So will exclude suspend/resume patch and will add patch for necessary write barrier fix in v8 version. Thanks Sowjanya
On Wed, Aug 7, 2019 at 5:40 AM Sowjanya Komatineni <skomatineni@nvidia.com> wrote: > On 8/6/19 2:51 PM, Sowjanya Komatineni wrote: > > > > On 8/5/19 2:20 AM, Linus Walleij wrote: > >> On Wed, Jul 31, 2019 at 11:11 PM Sowjanya Komatineni > >> <skomatineni@nvidia.com> wrote: > >> > >>> This patch adds support for Tegra pinctrl driver suspend and resume. > >>> > >>> During suspend, context of all pinctrl registers are stored and > >>> on resume they are all restored to have all the pinmux and pad > >>> configuration for normal operation. > >>> > >>> Acked-by: Thierry Reding <treding@nvidia.com> > >>> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> > >>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> > >> Patch applied to the pinctrl tree. > >> > >> This patch seems finished. > >> > >> Also if the rest don't get merged for v5.4 then at least this is so > >> your patch stack gets more shallow. > >> > >> I hope it's fine to merge this separately, else tell me and I'll > >> pull it out. > >> > >> Yours, > >> Linus Walleij > > > > Yes, this patch can be merged separately. But, there's latest feedback > > from Dmitry to add barrier after writes to make sure pinmux register > > writes happen. > > > > So will update this patch to add barrier in v8. So, need to wait for v8. > > > > Thanks > > > > Sowjanya > > > I see it merged. So will exclude suspend/resume patch and will add patch > for necessary write barrier fix in v8 version. Yeah just make an incremental patch, that's fine. If you want to overdo it you can add a Fixes: tag to the original patch, but I don't care much. Yours, Linus Walleij
diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c index 186ef98e7b2b..e3a237534281 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra.c +++ b/drivers/pinctrl/tegra/pinctrl-tegra.c @@ -631,6 +631,58 @@ static void tegra_pinctrl_clear_parked_bits(struct tegra_pmx *pmx) } } +static size_t tegra_pinctrl_get_bank_size(struct device *dev, + unsigned int bank_id) +{ + struct platform_device *pdev = to_platform_device(dev); + struct resource *res; + + res = platform_get_resource(pdev, IORESOURCE_MEM, bank_id); + + return resource_size(res) / 4; +} + +static int tegra_pinctrl_suspend(struct device *dev) +{ + struct tegra_pmx *pmx = dev_get_drvdata(dev); + u32 *backup_regs = pmx->backup_regs; + u32 *regs; + size_t bank_size; + unsigned int i, k; + + for (i = 0; i < pmx->nbanks; i++) { + bank_size = tegra_pinctrl_get_bank_size(dev, i); + regs = pmx->regs[i]; + for (k = 0; k < bank_size; k++) + *backup_regs++ = readl_relaxed(regs++); + } + + return pinctrl_force_sleep(pmx->pctl); +} + +static int tegra_pinctrl_resume(struct device *dev) +{ + struct tegra_pmx *pmx = dev_get_drvdata(dev); + u32 *backup_regs = pmx->backup_regs; + u32 *regs; + size_t bank_size; + unsigned int i, k; + + for (i = 0; i < pmx->nbanks; i++) { + bank_size = tegra_pinctrl_get_bank_size(dev, i); + regs = pmx->regs[i]; + for (k = 0; k < bank_size; k++) + writel_relaxed(*backup_regs++, regs++); + } + + return 0; +} + +const struct dev_pm_ops tegra_pinctrl_pm = { + .suspend = &tegra_pinctrl_suspend, + .resume = &tegra_pinctrl_resume +}; + static bool gpio_node_has_range(const char *compatible) { struct device_node *np; @@ -655,6 +707,7 @@ int tegra_pinctrl_probe(struct platform_device *pdev, int i; const char **group_pins; int fn, gn, gfn; + unsigned long backup_regs_size = 0; pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL); if (!pmx) @@ -707,6 +760,7 @@ int tegra_pinctrl_probe(struct platform_device *pdev, res = platform_get_resource(pdev, IORESOURCE_MEM, i); if (!res) break; + backup_regs_size += resource_size(res); } pmx->nbanks = i; @@ -715,6 +769,11 @@ int tegra_pinctrl_probe(struct platform_device *pdev, if (!pmx->regs) return -ENOMEM; + pmx->backup_regs = devm_kzalloc(&pdev->dev, backup_regs_size, + GFP_KERNEL); + if (!pmx->backup_regs) + return -ENOMEM; + for (i = 0; i < pmx->nbanks; i++) { res = platform_get_resource(pdev, IORESOURCE_MEM, i); pmx->regs[i] = devm_ioremap_resource(&pdev->dev, res); diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.h b/drivers/pinctrl/tegra/pinctrl-tegra.h index 105309774079..0fc82eea9cf1 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra.h +++ b/drivers/pinctrl/tegra/pinctrl-tegra.h @@ -17,6 +17,7 @@ struct tegra_pmx { int nbanks; void __iomem **regs; + u32 *backup_regs; }; enum tegra_pinconf_param { @@ -193,6 +194,8 @@ struct tegra_pinctrl_soc_data { bool drvtype_in_mux; }; +extern const struct dev_pm_ops tegra_pinctrl_pm; + int tegra_pinctrl_probe(struct platform_device *pdev, const struct tegra_pinctrl_soc_data *soc_data); #endif