From patchwork Wed Jul 31 21:11:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 1140098 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="WxNZMbGJ"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45zR1n0q3Cz9s3Z for ; Thu, 1 Aug 2019 07:11:41 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730594AbfGaVLL (ORCPT ); Wed, 31 Jul 2019 17:11:11 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:9218 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730534AbfGaVLL (ORCPT ); Wed, 31 Jul 2019 17:11:11 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Wed, 31 Jul 2019 14:11:19 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Wed, 31 Jul 2019 14:11:10 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Wed, 31 Jul 2019 14:11:10 -0700 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 31 Jul 2019 21:11:10 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 31 Jul 2019 21:11:09 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.110.102.167]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Wed, 31 Jul 2019 14:11:09 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , , , , , , , , , , , , Subject: [PATCH v7 18/20] soc/tegra: pmc: Configure deep sleep control settings Date: Wed, 31 Jul 2019 14:11:01 -0700 Message-ID: <1564607463-28802-19-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1564607463-28802-1-git-send-email-skomatineni@nvidia.com> References: <1564607463-28802-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1564607479; bh=e0L/CBaNsglm/ojFaoC8UfipD1BklMJFbKMEJWbcTJ0=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=WxNZMbGJr6f5ZolVCgTYwloWqM+HmNtxiGgHSlOOWEmOfbNJWTBGtlMoIhNwQF3KR eWu/hs1k8CiHZ4d+PlXro1Ci9g5aB/BpTUZYcM4GMcImP6BVAvZcIZM/vq22MRwHQs LxzRsZ/4XMIFgjZ/5H2hltylwhKbo4n+SS8ymEFn+l4FI1C8nfHn5dP2ovOHe2CAI+ 0tvY2tHwzR0ekfrKkxbjLSJcn0DWq/Iq16sEVnK7UFvJwti9kbN4Y5lbcsLEH48SfJ yUbtrhf6UjfqM/PqeuaZ0w9bHtC8wGkXXJMdeEJwzXKuRluzIjAgDGF4fY/A1GYbeZ Sn3XQz0qINuEA== Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Tegra210 and prior Tegra chips have deep sleep entry and wakeup related timings which are platform specific that should be configured before entering into deep sleep. Below are the timing specific configurations for deep sleep entry and wakeup. - Core rail power-on stabilization timer - OSC clock stabilization timer after SOC rail power is stabilized. - Core power off time is the minimum wake delay to keep the system in deep sleep state irrespective of any quick wake event. These values depends on the discharge time of regulators and turn OFF time of the PMIC to allow the complete system to finish entering into deep sleep state. These values vary based on the platform design and are specified through the device tree. This patch has implementation to configure these timings which are must to have for proper deep sleep and wakeup operations. Signed-off-by: Sowjanya Komatineni --- drivers/soc/tegra/pmc.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index e013ada7e4e9..9a78d8417367 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -88,6 +88,8 @@ #define PMC_CPUPWRGOOD_TIMER 0xc8 #define PMC_CPUPWROFF_TIMER 0xcc +#define PMC_COREPWRGOOD_TIMER 0x3c +#define PMC_COREPWROFF_TIMER 0xe0 #define PMC_PWR_DET_VALUE 0xe4 @@ -2277,7 +2279,7 @@ static const struct tegra_pmc_regs tegra20_pmc_regs = { static void tegra20_pmc_init(struct tegra_pmc *pmc) { - u32 value; + u32 value, osc, pmu, off; /* Always enable CPU power request */ value = tegra_pmc_readl(pmc, PMC_CNTRL); @@ -2303,6 +2305,15 @@ static void tegra20_pmc_init(struct tegra_pmc *pmc) value = tegra_pmc_readl(pmc, PMC_CNTRL); value |= PMC_CNTRL_SYSCLK_OE; tegra_pmc_writel(pmc, value, PMC_CNTRL); + + osc = DIV_ROUND_UP(pmc->core_osc_time * 8192, 1000000); + pmu = DIV_ROUND_UP(pmc->core_pmu_time * 32768, 1000000); + off = DIV_ROUND_UP(pmc->core_off_time * 32768, 1000000); + if (osc && pmu) + tegra_pmc_writel(pmc, ((osc << 8) & 0xff00) | (pmu & 0xff), + PMC_COREPWRGOOD_TIMER); + if (off) + tegra_pmc_writel(pmc, off, PMC_COREPWROFF_TIMER); } static void tegra20_pmc_setup_irq_polarity(struct tegra_pmc *pmc,