From patchwork Thu Sep 8 23:31:14 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kumar Gala X-Patchwork-Id: 114001 X-Patchwork-Delegate: galak@kernel.crashing.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 9FFDAB6F7C for ; Fri, 9 Sep 2011 09:31:39 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 37B1428298; Fri, 9 Sep 2011 01:31:36 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id MFe2wt6zmHbs; Fri, 9 Sep 2011 01:31:36 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 9C83E28299; Fri, 9 Sep 2011 01:31:32 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 51EF628299 for ; Fri, 9 Sep 2011 01:31:30 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id lqUtS3ojZcIE for ; Fri, 9 Sep 2011 01:31:28 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) by theia.denx.de (Postfix) with ESMTPS id A724C28298 for ; Fri, 9 Sep 2011 01:31:25 +0200 (CEST) Received: from localhost (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.13.8) with ESMTP id p88NVF0m004959; Thu, 8 Sep 2011 18:31:16 -0500 From: Kumar Gala To: u-boot@lists.denx.de Date: Thu, 8 Sep 2011 18:31:14 -0500 Message-Id: <1315524674-18244-1-git-send-email-galak@kernel.crashing.org> X-Mailer: git-send-email 1.5.6.5 Cc: Santosh Shukla Subject: [U-Boot] [PATCH] powerpc/85xx: Add support for setting up RAID engine liodns on P5020 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Santosh Shukla Add support for Job Queue/Ring LIODN for the RAID Engine on P5020. Each Job Queue/Ring combo needs one id assigned for a total of 4 (2 JQs/2 Rings per JQ). This just handles RAID Engine in non-DPAA mode. Signed-off-by: Santosh Shukla Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc85xx/liodn.c | 25 ++++++++++++++++++++++++- arch/powerpc/cpu/mpc85xx/p5020_ids.c | 13 +++++++++++++ arch/powerpc/include/asm/fsl_liodn.h | 11 ++++++++++- arch/powerpc/include/asm/fsl_portals.h | 3 +++ arch/powerpc/include/asm/immap_85xx.h | 19 +++++++++++++++++++ include/configs/P5020DS.h | 1 + 6 files changed, 70 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/liodn.c b/arch/powerpc/cpu/mpc85xx/liodn.c index bd19094..6f0a2a7 100644 --- a/arch/powerpc/cpu/mpc85xx/liodn.c +++ b/arch/powerpc/cpu/mpc85xx/liodn.c @@ -1,5 +1,5 @@ /* - * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008-2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -120,6 +120,19 @@ static void setup_pme_liodn_base(void) #endif } +#ifdef CONFIG_SYS_FSL_RAID_ENGINE +static void setup_raide_liodn_base(void) +{ + ccsr_raide_t *raide = (void *)CONFIG_SYS_FSL_RAID_ENGINE_ADDR; + + /* setup raid engine liodn base for data/desc ; both set to 47 */ + u32 base = (liodn_bases[FSL_HW_PORTAL_RAID_ENGINE].id[0] << 16) | + liodn_bases[FSL_HW_PORTAL_RAID_ENGINE].id[0]; + + out_be32(&raide->liodnbr, base); +} +#endif + void set_liodns(void) { /* setup general liodn offsets */ @@ -145,6 +158,12 @@ void set_liodns(void) #endif /* setup PME liodn base */ setup_pme_liodn_base(); + +#ifdef CONFIG_SYS_FSL_RAID_ENGINE + /* raid engine ccr addr code for liodn */ + set_liodn(raide_liodn_tbl, raide_liodn_tbl_sz); + setup_raide_liodn_base(); +#endif } static void fdt_fixup_liodn_tbl(void *blob, struct liodn_id_table *tbl, int sz) @@ -184,4 +203,8 @@ void fdt_fixup_liodn(void *blob) #endif #endif fdt_fixup_liodn_tbl(blob, sec_liodn_tbl, sec_liodn_tbl_sz); + +#ifdef CONFIG_SYS_FSL_RAID_ENGINE + fdt_fixup_liodn_tbl(blob, raide_liodn_tbl, raide_liodn_tbl_sz); +#endif } diff --git a/arch/powerpc/cpu/mpc85xx/p5020_ids.c b/arch/powerpc/cpu/mpc85xx/p5020_ids.c index 9836588..2911c13 100644 --- a/arch/powerpc/cpu/mpc85xx/p5020_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p5020_ids.c @@ -97,6 +97,16 @@ struct liodn_id_table sec_liodn_tbl[] = { }; int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl); +#ifdef CONFIG_SYS_FSL_RAID_ENGINE +struct liodn_id_table raide_liodn_tbl[] = { + SET_RAID_ENGINE_JQ_LIODN_ENTRY(0, 0, 60), + SET_RAID_ENGINE_JQ_LIODN_ENTRY(0, 1, 61), + SET_RAID_ENGINE_JQ_LIODN_ENTRY(1, 0, 62), + SET_RAID_ENGINE_JQ_LIODN_ENTRY(1, 1, 63), +}; +int raide_liodn_tbl_sz = ARRAY_SIZE(raide_liodn_tbl); +#endif + struct liodn_id_table liodn_bases[] = { [FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(64, 100), #ifdef CONFIG_SYS_DPAA_FMAN @@ -105,4 +115,7 @@ struct liodn_id_table liodn_bases[] = { #ifdef CONFIG_SYS_DPAA_PME [FSL_HW_PORTAL_PME] = SET_LIODN_BASE_2(136, 172), #endif +#ifdef CONFIG_SYS_FSL_RAID_ENGINE + [FSL_HW_PORTAL_RAID_ENGINE] = SET_LIODN_BASE_1(47), +#endif }; diff --git a/arch/powerpc/include/asm/fsl_liodn.h b/arch/powerpc/include/asm/fsl_liodn.h index 801571f..7f7040f 100644 --- a/arch/powerpc/include/asm/fsl_liodn.h +++ b/arch/powerpc/include/asm/fsl_liodn.h @@ -147,9 +147,18 @@ extern void fdt_fixup_liodn(void *blob); offsetof(ccsr_sec_t, decoliodnr[num].ls) + \ CONFIG_SYS_FSL_SEC_OFFSET, 0) +#define SET_RAID_ENGINE_JQ_LIODN_ENTRY(jqNum, rNum, liodnA) \ + SET_LIODN_ENTRY_1("fsl,raideng-v1.0-job-ring", \ + liodnA, \ + offsetof(ccsr_raide_t, jq[jqNum].ring[rNum].cfg1) + \ + CONFIG_SYS_FSL_RAID_ENGINE_OFFSET, \ + offsetof(ccsr_raide_t, jq[jqNum].ring[rNum].cfg0) + \ + CONFIG_SYS_FSL_RAID_ENGINE_OFFSET) + extern struct liodn_id_table liodn_tbl[], liodn_bases[], sec_liodn_tbl[]; +extern struct liodn_id_table raide_liodn_tbl[]; extern struct liodn_id_table fman1_liodn_tbl[], fman2_liodn_tbl[]; -extern int liodn_tbl_sz, sec_liodn_tbl_sz; +extern int liodn_tbl_sz, sec_liodn_tbl_sz, raide_liodn_tbl_sz; extern int fman1_liodn_tbl_sz, fman2_liodn_tbl_sz; #endif diff --git a/arch/powerpc/include/asm/fsl_portals.h b/arch/powerpc/include/asm/fsl_portals.h index e1c1212..8c3ea0b 100644 --- a/arch/powerpc/include/asm/fsl_portals.h +++ b/arch/powerpc/include/asm/fsl_portals.h @@ -35,6 +35,9 @@ enum fsl_dpaa_dev { #ifdef CONFIG_SYS_DPAA_PME FSL_HW_PORTAL_PME, #endif +#ifdef CONFIG_SYS_FSL_RAID_ENGINE + FSL_HW_PORTAL_RAID_ENGINE, +#endif }; struct qportal_info { diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index d4fdd10..4aa8dcc 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -2324,6 +2324,22 @@ typedef struct ccsr_usb_phy { } ccsr_usb_phy_t; #define CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE 1 +#ifdef CONFIG_SYS_FSL_RAID_ENGINE +typedef struct ccsr_raide { + u8 res0[0x543]; + u32 liodnbr; /* LIODN Base Register */ + u8 res1[0xab8]; + struct { + struct { + u32 cfg0; /* cfg register 0 */ + u32 cfg1; /* cfg register 1 */ + u8 res1[0x3f8]; + } ring[2]; + u8 res[0x800]; + } jq[2]; +} ccsr_raide_t; +#endif + #ifdef CONFIG_SECURE_BOOT typedef struct ccsr_sfp_regs { u8 reserved0[0x40]; @@ -2390,6 +2406,7 @@ typedef struct ccsr_snvs_regs { #define CONFIG_SYS_FSL_CORENET_PME_OFFSET 0x316000 #define CONFIG_SYS_FSL_QMAN_OFFSET 0x318000 #define CONFIG_SYS_FSL_BMAN_OFFSET 0x31a000 +#define CONFIG_SYS_FSL_RAID_ENGINE_OFFSET 0x320000 #define CONFIG_SYS_FSL_FM1_OFFSET 0x400000 #define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0x488000 #define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0x489000 @@ -2460,6 +2477,8 @@ typedef struct ccsr_snvs_regs { (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_BMAN_OFFSET) #define CONFIG_SYS_FSL_CORENET_PME_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_PME_OFFSET) +#define CONFIG_SYS_FSL_RAID_ENGINE_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_RAID_ENGINE_OFFSET) #define CONFIG_SYS_MPC85xx_GUTS_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GUTS_OFFSET) #define CONFIG_SYS_FSL_CORENET_CCM_ADDR \ diff --git a/include/configs/P5020DS.h b/include/configs/P5020DS.h index dd8d442..2c7beba 100644 --- a/include/configs/P5020DS.h +++ b/include/configs/P5020DS.h @@ -30,6 +30,7 @@ #define CONFIG_FSL_SATA_V2 #define CONFIG_PCIE4 +#define CONFIG_SYS_FSL_RAID_ENGINE #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */