Patchwork [U-Boot] powerpc/85xx: Add support for setting up RAID engine liodns on P5020

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Submitter Kumar Gala
Date Sept. 8, 2011, 11:31 p.m.
Message ID <1315524674-18244-1-git-send-email-galak@kernel.crashing.org>
Download mbox | patch
Permalink /patch/114001/
State Superseded
Delegated to: Kumar Gala
Headers show

Comments

Kumar Gala - Sept. 8, 2011, 11:31 p.m.
From: Santosh Shukla <santosh.shukla@freescale.com>

Add support for Job Queue/Ring LIODN for the RAID Engine on P5020.  Each
Job Queue/Ring combo needs one id assigned for a total of 4 (2 JQs/2
Rings per JQ).  This just handles RAID Engine in non-DPAA mode.

Signed-off-by: Santosh Shukla <santosh.shukla@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
 arch/powerpc/cpu/mpc85xx/liodn.c       |   25 ++++++++++++++++++++++++-
 arch/powerpc/cpu/mpc85xx/p5020_ids.c   |   13 +++++++++++++
 arch/powerpc/include/asm/fsl_liodn.h   |   11 ++++++++++-
 arch/powerpc/include/asm/fsl_portals.h |    3 +++
 arch/powerpc/include/asm/immap_85xx.h  |   19 +++++++++++++++++++
 include/configs/P5020DS.h              |    1 +
 6 files changed, 70 insertions(+), 2 deletions(-)

Patch

diff --git a/arch/powerpc/cpu/mpc85xx/liodn.c b/arch/powerpc/cpu/mpc85xx/liodn.c
index bd19094..6f0a2a7 100644
--- a/arch/powerpc/cpu/mpc85xx/liodn.c
+++ b/arch/powerpc/cpu/mpc85xx/liodn.c
@@ -1,5 +1,5 @@ 
 /*
- * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ * Copyright 2008-2011 Freescale Semiconductor, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -120,6 +120,19 @@  static void setup_pme_liodn_base(void)
 #endif
 }
 
+#ifdef CONFIG_SYS_FSL_RAID_ENGINE
+static void setup_raide_liodn_base(void)
+{
+	ccsr_raide_t *raide = (void *)CONFIG_SYS_FSL_RAID_ENGINE_ADDR;
+
+	/* setup raid engine liodn base for data/desc ; both set to 47 */
+	u32 base = (liodn_bases[FSL_HW_PORTAL_RAID_ENGINE].id[0] << 16) |
+			liodn_bases[FSL_HW_PORTAL_RAID_ENGINE].id[0];
+
+	out_be32(&raide->liodnbr, base);
+}
+#endif
+
 void set_liodns(void)
 {
 	/* setup general liodn offsets */
@@ -145,6 +158,12 @@  void set_liodns(void)
 #endif
 	/* setup PME liodn base */
 	setup_pme_liodn_base();
+
+#ifdef CONFIG_SYS_FSL_RAID_ENGINE
+	/* raid engine ccr addr code for liodn */
+	set_liodn(raide_liodn_tbl, raide_liodn_tbl_sz);
+	setup_raide_liodn_base();
+#endif
 }
 
 static void fdt_fixup_liodn_tbl(void *blob, struct liodn_id_table *tbl, int sz)
@@ -184,4 +203,8 @@  void fdt_fixup_liodn(void *blob)
 #endif
 #endif
 	fdt_fixup_liodn_tbl(blob, sec_liodn_tbl, sec_liodn_tbl_sz);
+
+#ifdef CONFIG_SYS_FSL_RAID_ENGINE
+	fdt_fixup_liodn_tbl(blob, raide_liodn_tbl, raide_liodn_tbl_sz);
+#endif
 }
diff --git a/arch/powerpc/cpu/mpc85xx/p5020_ids.c b/arch/powerpc/cpu/mpc85xx/p5020_ids.c
index 9836588..2911c13 100644
--- a/arch/powerpc/cpu/mpc85xx/p5020_ids.c
+++ b/arch/powerpc/cpu/mpc85xx/p5020_ids.c
@@ -97,6 +97,16 @@  struct liodn_id_table sec_liodn_tbl[] = {
 };
 int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl);
 
+#ifdef CONFIG_SYS_FSL_RAID_ENGINE
+struct liodn_id_table raide_liodn_tbl[] = {
+	SET_RAID_ENGINE_JQ_LIODN_ENTRY(0, 0, 60),
+	SET_RAID_ENGINE_JQ_LIODN_ENTRY(0, 1, 61),
+	SET_RAID_ENGINE_JQ_LIODN_ENTRY(1, 0, 62),
+	SET_RAID_ENGINE_JQ_LIODN_ENTRY(1, 1, 63),
+};
+int raide_liodn_tbl_sz = ARRAY_SIZE(raide_liodn_tbl);
+#endif
+
 struct liodn_id_table liodn_bases[] = {
 	[FSL_HW_PORTAL_SEC]  = SET_LIODN_BASE_2(64, 100),
 #ifdef CONFIG_SYS_DPAA_FMAN
@@ -105,4 +115,7 @@  struct liodn_id_table liodn_bases[] = {
 #ifdef CONFIG_SYS_DPAA_PME
 	[FSL_HW_PORTAL_PME]   = SET_LIODN_BASE_2(136, 172),
 #endif
+#ifdef CONFIG_SYS_FSL_RAID_ENGINE
+	[FSL_HW_PORTAL_RAID_ENGINE]  = SET_LIODN_BASE_1(47),
+#endif
 };
diff --git a/arch/powerpc/include/asm/fsl_liodn.h b/arch/powerpc/include/asm/fsl_liodn.h
index 801571f..7f7040f 100644
--- a/arch/powerpc/include/asm/fsl_liodn.h
+++ b/arch/powerpc/include/asm/fsl_liodn.h
@@ -147,9 +147,18 @@  extern void fdt_fixup_liodn(void *blob);
 		offsetof(ccsr_sec_t, decoliodnr[num].ls) + \
 		CONFIG_SYS_FSL_SEC_OFFSET, 0)
 
+#define SET_RAID_ENGINE_JQ_LIODN_ENTRY(jqNum, rNum, liodnA) \
+	SET_LIODN_ENTRY_1("fsl,raideng-v1.0-job-ring", \
+	liodnA, \
+	offsetof(ccsr_raide_t, jq[jqNum].ring[rNum].cfg1) + \
+	CONFIG_SYS_FSL_RAID_ENGINE_OFFSET, \
+	offsetof(ccsr_raide_t, jq[jqNum].ring[rNum].cfg0) + \
+	CONFIG_SYS_FSL_RAID_ENGINE_OFFSET)
+
 extern struct liodn_id_table liodn_tbl[], liodn_bases[], sec_liodn_tbl[];
+extern struct liodn_id_table raide_liodn_tbl[];
 extern struct liodn_id_table fman1_liodn_tbl[], fman2_liodn_tbl[];
-extern int liodn_tbl_sz, sec_liodn_tbl_sz;
+extern int liodn_tbl_sz, sec_liodn_tbl_sz, raide_liodn_tbl_sz;
 extern int fman1_liodn_tbl_sz, fman2_liodn_tbl_sz;
 
 #endif
diff --git a/arch/powerpc/include/asm/fsl_portals.h b/arch/powerpc/include/asm/fsl_portals.h
index e1c1212..8c3ea0b 100644
--- a/arch/powerpc/include/asm/fsl_portals.h
+++ b/arch/powerpc/include/asm/fsl_portals.h
@@ -35,6 +35,9 @@  enum fsl_dpaa_dev {
 #ifdef CONFIG_SYS_DPAA_PME
 	FSL_HW_PORTAL_PME,
 #endif
+#ifdef CONFIG_SYS_FSL_RAID_ENGINE
+	FSL_HW_PORTAL_RAID_ENGINE,
+#endif
 };
 
 struct qportal_info {
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index d4fdd10..4aa8dcc 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -2324,6 +2324,22 @@  typedef struct ccsr_usb_phy {
 } ccsr_usb_phy_t;
 #define CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE 1
 
+#ifdef CONFIG_SYS_FSL_RAID_ENGINE
+typedef struct ccsr_raide {
+	u8	res0[0x543];
+	u32	liodnbr;			/* LIODN Base Register */
+	u8	res1[0xab8];
+	struct {
+		struct {
+			u32	cfg0;		/* cfg register 0 */
+			u32	cfg1;		/* cfg register 1 */
+			u8	res1[0x3f8];
+		} ring[2];
+		u8	res[0x800];
+	} jq[2];
+} ccsr_raide_t;
+#endif
+
 #ifdef CONFIG_SECURE_BOOT
 typedef struct ccsr_sfp_regs {
 	u8 reserved0[0x40];
@@ -2390,6 +2406,7 @@  typedef struct ccsr_snvs_regs {
 #define CONFIG_SYS_FSL_CORENET_PME_OFFSET	0x316000
 #define CONFIG_SYS_FSL_QMAN_OFFSET		0x318000
 #define CONFIG_SYS_FSL_BMAN_OFFSET		0x31a000
+#define CONFIG_SYS_FSL_RAID_ENGINE_OFFSET	0x320000
 #define CONFIG_SYS_FSL_FM1_OFFSET		0x400000
 #define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET	0x488000
 #define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET	0x489000
@@ -2460,6 +2477,8 @@  typedef struct ccsr_snvs_regs {
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_BMAN_OFFSET)
 #define CONFIG_SYS_FSL_CORENET_PME_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_PME_OFFSET)
+#define CONFIG_SYS_FSL_RAID_ENGINE_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_RAID_ENGINE_OFFSET)
 #define CONFIG_SYS_MPC85xx_GUTS_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GUTS_OFFSET)
 #define CONFIG_SYS_FSL_CORENET_CCM_ADDR \
diff --git a/include/configs/P5020DS.h b/include/configs/P5020DS.h
index dd8d442..2c7beba 100644
--- a/include/configs/P5020DS.h
+++ b/include/configs/P5020DS.h
@@ -30,6 +30,7 @@ 
 
 #define CONFIG_FSL_SATA_V2
 #define CONFIG_PCIE4
+#define CONFIG_SYS_FSL_RAID_ENGINE
 
 #define CONFIG_ICS307_REFCLK_HZ		25000000  /* ICS307 ref clk freq */