From patchwork Thu Jul 25 04:30:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Hung X-Patchwork-Id: 1136661 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.ubuntu.com (client-ip=91.189.94.19; helo=huckleberry.canonical.com; envelope-from=fwts-devel-bounces@lists.ubuntu.com; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=canonical.com Received: from huckleberry.canonical.com (huckleberry.canonical.com [91.189.94.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 45vK5Q1MLJz9sBt; Thu, 25 Jul 2019 14:30:33 +1000 (AEST) Received: from localhost ([127.0.0.1] helo=huckleberry.canonical.com) by huckleberry.canonical.com with esmtp (Exim 4.86_2) (envelope-from ) id 1hqVOg-0002i8-Ps; Thu, 25 Jul 2019 04:30:30 +0000 Received: from youngberry.canonical.com ([91.189.89.112]) by huckleberry.canonical.com with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:128) (Exim 4.86_2) (envelope-from ) id 1hqVOf-0002i2-AO for fwts-devel@lists.ubuntu.com; Thu, 25 Jul 2019 04:30:29 +0000 Received: from 1.general.alexhung.us.vpn ([10.172.65.254] helo=canonical.com) by youngberry.canonical.com with esmtpsa (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.76) (envelope-from ) id 1hqVOe-0004B1-L3; Thu, 25 Jul 2019 04:30:29 +0000 From: Alex Hung To: fwts-devel@lists.ubuntu.com Subject: [PATCH 5/5] cpu/msr: update MISC_ENABLE to IA32_silvermont_MSRs Date: Wed, 24 Jul 2019 22:30:26 -0600 Message-Id: <20190725043026.2125-1-alex.hung@canonical.com> X-Mailer: git-send-email 2.17.1 X-BeenThere: fwts-devel@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Firmware Test Suite Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: fwts-devel-bounces@lists.ubuntu.com Sender: "fwts-devel" MISC_ENABLE in silvermont has one more feature than the one defined in architectural MSRs (IA32_MSRs): BIT38 - Turbo Mode Disable (R/W). Signed-off-by: Alex Hung Acked-by: Colin Ian King Acked-by: Ivan Hu --- src/cpu/msr/msr.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/cpu/msr/msr.c b/src/cpu/msr/msr.c index daa75d57..2fdf4d99 100644 --- a/src/cpu/msr/msr.c +++ b/src/cpu/msr/msr.c @@ -484,6 +484,7 @@ static const msr_info IA32_silvermont_MSRs[] = { { "MSR_PMG_IO_CAPTURE_BASE", 0x000000e4, 0x000000000007ffffULL, NULL }, { "MSR_BBL_CR_CTL3", 0x0000011e, 0x0000000000800101ULL, NULL }, { "MSR_FEATURE_CONFIG", 0x0000013c, 0x0000000000000003ULL, NULL }, + { "MISC_ENABLE", 0x000001a0, 0x0000004400c51889ULL, NULL }, { "MSR_TEMPERATURE_TARGET", 0x000001a2, 0x000000003fff0000ULL, NULL }, { NULL, 0x00000000, 0, NULL }, };