[5/5] cpu/msr: update MISC_ENABLE to IA32_silvermont_MSRs
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Message ID 20190725043026.2125-1-alex.hung@canonical.com
State Accepted
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Series
  • Untitled series #121355
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Commit Message

Alex Hung July 25, 2019, 4:30 a.m. UTC
MISC_ENABLE in silvermont has one more feature than the one defined in
architectural MSRs (IA32_MSRs): BIT38 - Turbo Mode Disable (R/W).

Signed-off-by: Alex Hung <alex.hung@canonical.com>
---
 src/cpu/msr/msr.c | 1 +
 1 file changed, 1 insertion(+)

Comments

Colin King July 25, 2019, 7:01 a.m. UTC | #1
On 25/07/2019 05:30, Alex Hung wrote:
> MISC_ENABLE in silvermont has one more feature than the one defined in
> architectural MSRs (IA32_MSRs): BIT38 - Turbo Mode Disable (R/W).
> 
> Signed-off-by: Alex Hung <alex.hung@canonical.com>
> ---
>  src/cpu/msr/msr.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/src/cpu/msr/msr.c b/src/cpu/msr/msr.c
> index daa75d57..2fdf4d99 100644
> --- a/src/cpu/msr/msr.c
> +++ b/src/cpu/msr/msr.c
> @@ -484,6 +484,7 @@ static const msr_info IA32_silvermont_MSRs[] = {
>  	{ "MSR_PMG_IO_CAPTURE_BASE",	0x000000e4,	0x000000000007ffffULL, NULL },
>  	{ "MSR_BBL_CR_CTL3",		0x0000011e,	0x0000000000800101ULL, NULL },
>  	{ "MSR_FEATURE_CONFIG",		0x0000013c,	0x0000000000000003ULL, NULL },
> +	{ "MISC_ENABLE",		0x000001a0,	0x0000004400c51889ULL, NULL },
>  	{ "MSR_TEMPERATURE_TARGET",	0x000001a2,	0x000000003fff0000ULL, NULL },
>  	{ NULL,				0x00000000,	0, NULL },
>  };
> 

Acked-by: Colin Ian King <colin.king@canonical.com>
ivanhu July 25, 2019, 8:05 a.m. UTC | #2
On 7/25/19 12:30 PM, Alex Hung wrote:
> MISC_ENABLE in silvermont has one more feature than the one defined in
> architectural MSRs (IA32_MSRs): BIT38 - Turbo Mode Disable (R/W).
>
> Signed-off-by: Alex Hung <alex.hung@canonical.com>
> ---
>  src/cpu/msr/msr.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/src/cpu/msr/msr.c b/src/cpu/msr/msr.c
> index daa75d57..2fdf4d99 100644
> --- a/src/cpu/msr/msr.c
> +++ b/src/cpu/msr/msr.c
> @@ -484,6 +484,7 @@ static const msr_info IA32_silvermont_MSRs[] = {
>  	{ "MSR_PMG_IO_CAPTURE_BASE",	0x000000e4,	0x000000000007ffffULL, NULL },
>  	{ "MSR_BBL_CR_CTL3",		0x0000011e,	0x0000000000800101ULL, NULL },
>  	{ "MSR_FEATURE_CONFIG",		0x0000013c,	0x0000000000000003ULL, NULL },
> +	{ "MISC_ENABLE",		0x000001a0,	0x0000004400c51889ULL, NULL },
>  	{ "MSR_TEMPERATURE_TARGET",	0x000001a2,	0x000000003fff0000ULL, NULL },
>  	{ NULL,				0x00000000,	0, NULL },
>  };
Acked-by: Ivan Hu <ivan.hu@canonical.com>

Patch
diff mbox series

diff --git a/src/cpu/msr/msr.c b/src/cpu/msr/msr.c
index daa75d57..2fdf4d99 100644
--- a/src/cpu/msr/msr.c
+++ b/src/cpu/msr/msr.c
@@ -484,6 +484,7 @@  static const msr_info IA32_silvermont_MSRs[] = {
 	{ "MSR_PMG_IO_CAPTURE_BASE",	0x000000e4,	0x000000000007ffffULL, NULL },
 	{ "MSR_BBL_CR_CTL3",		0x0000011e,	0x0000000000800101ULL, NULL },
 	{ "MSR_FEATURE_CONFIG",		0x0000013c,	0x0000000000000003ULL, NULL },
+	{ "MISC_ENABLE",		0x000001a0,	0x0000004400c51889ULL, NULL },
 	{ "MSR_TEMPERATURE_TARGET",	0x000001a2,	0x000000003fff0000ULL, NULL },
 	{ NULL,				0x00000000,	0, NULL },
 };