[01/11] dt-bindings: timer: Convert Allwinner A10 Timer to a schema
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Message ID 20190722081229.22422-1-maxime.ripard@bootlin.com
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  • [01/11] dt-bindings: timer: Convert Allwinner A10 Timer to a schema
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Commit Message

Maxime Ripard July 22, 2019, 8:12 a.m. UTC
The older Allwinner SoCs have a Timer supported in Linux, with a matching
Device Tree binding.

While the original binding only mentions one interrupt, the timer actually
has 6 of them.

Now that we have the DT validation in place, let's convert the device tree
bindings for that controller over to a YAML schemas.

Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
---
 .../timer/allwinner,sun4i-a10-timer.yaml      | 76 +++++++++++++++++++
 .../bindings/timer/allwinner,sun4i-timer.txt  | 19 -----
 2 files changed, 76 insertions(+), 19 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml
 delete mode 100644 Documentation/devicetree/bindings/timer/allwinner,sun4i-timer.txt

Comments

Rob Herring July 22, 2019, 3:05 p.m. UTC | #1
On Mon, Jul 22, 2019 at 2:12 AM Maxime Ripard <maxime.ripard@bootlin.com> wrote:
>
> The older Allwinner SoCs have a Timer supported in Linux, with a matching
> Device Tree binding.
>
> While the original binding only mentions one interrupt, the timer actually
> has 6 of them.
>
> Now that we have the DT validation in place, let's convert the device tree
> bindings for that controller over to a YAML schemas.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
> ---
>  .../timer/allwinner,sun4i-a10-timer.yaml      | 76 +++++++++++++++++++
>  .../bindings/timer/allwinner,sun4i-timer.txt  | 19 -----
>  2 files changed, 76 insertions(+), 19 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml
>  delete mode 100644 Documentation/devicetree/bindings/timer/allwinner,sun4i-timer.txt

Reviewed-by: Rob Herring <robh@kernel.org>
Maxime Ripard Aug. 12, 2019, 8:58 a.m. UTC | #2
Hi Daniel, Thomas,

On Mon, Jul 22, 2019 at 10:12:21AM +0200, Maxime Ripard wrote:
> Newer Allwinner SoCs have different number of interrupts, let's add
> different compatibles for all of them to deal with this properly.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>

Ping?

Maxime

--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
Daniel Lezcano Aug. 12, 2019, 8:59 a.m. UTC | #3
On 22/07/2019 10:12, Maxime Ripard wrote:
> Newer Allwinner SoCs have different number of interrupts, let's add
> different compatibles for all of them to deal with this properly.
> 
> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>

Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>

> ---
>  drivers/clocksource/timer-sun4i.c | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/clocksource/timer-sun4i.c b/drivers/clocksource/timer-sun4i.c
> index 65f38f6ca714..0ba8155b8287 100644
> --- a/drivers/clocksource/timer-sun4i.c
> +++ b/drivers/clocksource/timer-sun4i.c
> @@ -219,5 +219,9 @@ static int __init sun4i_timer_init(struct device_node *node)
>  }
>  TIMER_OF_DECLARE(sun4i, "allwinner,sun4i-a10-timer",
>  		       sun4i_timer_init);
> +TIMER_OF_DECLARE(sun8i_a23, "allwinner,sun8i-a23-timer",
> +		 sun4i_timer_init);
> +TIMER_OF_DECLARE(sun8i_v3s, "allwinner,sun8i-v3s-timer",
> +		 sun4i_timer_init);
>  TIMER_OF_DECLARE(suniv, "allwinner,suniv-f1c100s-timer",
>  		       sun4i_timer_init);
>
Maxime Ripard Aug. 12, 2019, 9:16 a.m. UTC | #4
Hi,

On Mon, Aug 12, 2019 at 10:59:51AM +0200, Daniel Lezcano wrote:
> On 22/07/2019 10:12, Maxime Ripard wrote:
> > Newer Allwinner SoCs have different number of interrupts, let's add
> > different compatibles for all of them to deal with this properly.
> >
> > Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
>
> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>

Thanks!

Can you merge this through your tree (along with the bindings)? I'll
merge the DT patches

Maxime

--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
Daniel Lezcano Aug. 12, 2019, 9:21 a.m. UTC | #5
On 12/08/2019 11:16, Maxime Ripard wrote:
> Hi,
> 
> On Mon, Aug 12, 2019 at 10:59:51AM +0200, Daniel Lezcano wrote:
>> On 22/07/2019 10:12, Maxime Ripard wrote:
>>> Newer Allwinner SoCs have different number of interrupts, let's add
>>> different compatibles for all of them to deal with this properly.
>>>
>>> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
>>
>> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
> 
> Thanks!
> 
> Can you merge this through your tree (along with the bindings)? I'll
> merge the DT patches

patches 1-4 then ?
Maxime Ripard Aug. 12, 2019, 11:24 a.m. UTC | #6
On Mon, Aug 12, 2019 at 11:21:50AM +0200, Daniel Lezcano wrote:
> On 12/08/2019 11:16, Maxime Ripard wrote:
> > Hi,
> >
> > On Mon, Aug 12, 2019 at 10:59:51AM +0200, Daniel Lezcano wrote:
> >> On 22/07/2019 10:12, Maxime Ripard wrote:
> >>> Newer Allwinner SoCs have different number of interrupts, let's add
> >>> different compatibles for all of them to deal with this properly.
> >>>
> >>> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
> >>
> >> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
> >
> > Thanks!
> >
> > Can you merge this through your tree (along with the bindings)? I'll
> > merge the DT patches
>
> patches 1-4 then ?

Yep, thanks!
Maxime

--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
Maxime Ripard Aug. 19, 2019, 1:30 p.m. UTC | #7
On Mon, Aug 12, 2019 at 01:24:11PM +0200, Maxime Ripard wrote:
> On Mon, Aug 12, 2019 at 11:21:50AM +0200, Daniel Lezcano wrote:
> > On 12/08/2019 11:16, Maxime Ripard wrote:
> > > Hi,
> > >
> > > On Mon, Aug 12, 2019 at 10:59:51AM +0200, Daniel Lezcano wrote:
> > >> On 22/07/2019 10:12, Maxime Ripard wrote:
> > >>> Newer Allwinner SoCs have different number of interrupts, let's add
> > >>> different compatibles for all of them to deal with this properly.
> > >>>
> > >>> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
> > >>
> > >> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
> > >
> > > Thanks!
> > >
> > > Can you merge this through your tree (along with the bindings)? I'll
> > > merge the DT patches
> >
> > patches 1-4 then ?
>
> Yep, thanks!

Ping?

Maxime

--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
Daniel Lezcano Aug. 19, 2019, 1:45 p.m. UTC | #8
On 19/08/2019 15:30, Maxime Ripard wrote:
> On Mon, Aug 12, 2019 at 01:24:11PM +0200, Maxime Ripard wrote:
>> On Mon, Aug 12, 2019 at 11:21:50AM +0200, Daniel Lezcano wrote:
>>> On 12/08/2019 11:16, Maxime Ripard wrote:
>>>> Hi,
>>>>
>>>> On Mon, Aug 12, 2019 at 10:59:51AM +0200, Daniel Lezcano wrote:
>>>>> On 22/07/2019 10:12, Maxime Ripard wrote:
>>>>>> Newer Allwinner SoCs have different number of interrupts, let's add
>>>>>> different compatibles for all of them to deal with this properly.
>>>>>>
>>>>>> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
>>>>>
>>>>> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
>>>>
>>>> Thanks!
>>>>
>>>> Can you merge this through your tree (along with the bindings)? I'll
>>>> merge the DT patches
>>>
>>> patches 1-4 then ?
>>
>> Yep, thanks!
> 
> Ping?

They are applied :)
Maxime Ripard Aug. 19, 2019, 7:13 p.m. UTC | #9
On Mon, Aug 19, 2019 at 03:45:40PM +0200, Daniel Lezcano wrote:
> On 19/08/2019 15:30, Maxime Ripard wrote:
> > On Mon, Aug 12, 2019 at 01:24:11PM +0200, Maxime Ripard wrote:
> >> On Mon, Aug 12, 2019 at 11:21:50AM +0200, Daniel Lezcano wrote:
> >>> On 12/08/2019 11:16, Maxime Ripard wrote:
> >>>> Hi,
> >>>>
> >>>> On Mon, Aug 12, 2019 at 10:59:51AM +0200, Daniel Lezcano wrote:
> >>>>> On 22/07/2019 10:12, Maxime Ripard wrote:
> >>>>>> Newer Allwinner SoCs have different number of interrupts, let's add
> >>>>>> different compatibles for all of them to deal with this properly.
> >>>>>>
> >>>>>> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
> >>>>>
> >>>>> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
> >>>>
> >>>> Thanks!
> >>>>
> >>>> Can you merge this through your tree (along with the bindings)? I'll
> >>>> merge the DT patches
> >>>
> >>> patches 1-4 then ?
> >>
> >> Yep, thanks!
> >
> > Ping?
>
> They are applied :)

Oh, my bad :)

Where is your tree these days? I couldn't find it in linux-next either
:/

Thanks!
Maxime

--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
Daniel Lezcano Aug. 19, 2019, 7:43 p.m. UTC | #10
On 19/08/2019 21:13, Maxime Ripard wrote:
> On Mon, Aug 19, 2019 at 03:45:40PM +0200, Daniel Lezcano wrote:
>> On 19/08/2019 15:30, Maxime Ripard wrote:
>>> On Mon, Aug 12, 2019 at 01:24:11PM +0200, Maxime Ripard wrote:
>>>> On Mon, Aug 12, 2019 at 11:21:50AM +0200, Daniel Lezcano wrote:
>>>>> On 12/08/2019 11:16, Maxime Ripard wrote:
>>>>>> Hi,
>>>>>>
>>>>>> On Mon, Aug 12, 2019 at 10:59:51AM +0200, Daniel Lezcano wrote:
>>>>>>> On 22/07/2019 10:12, Maxime Ripard wrote:
>>>>>>>> Newer Allwinner SoCs have different number of interrupts, let's add
>>>>>>>> different compatibles for all of them to deal with this properly.
>>>>>>>>
>>>>>>>> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
>>>>>>>
>>>>>>> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
>>>>>>
>>>>>> Thanks!
>>>>>>
>>>>>> Can you merge this through your tree (along with the bindings)? I'll
>>>>>> merge the DT patches
>>>>>
>>>>> patches 1-4 then ?
>>>>
>>>> Yep, thanks!
>>>
>>> Ping?
>>
>> They are applied :)
> 
> Oh, my bad :)

Actually, I should have tell you they were applied.

> Where is your tree these days? I couldn't find it in linux-next either

https://git.linaro.org/people/daniel.lezcano/linux.git/log/?h=clockevents/next

Patch
diff mbox series

diff --git a/Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml b/Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml
new file mode 100644
index 000000000000..7292a424092c
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml
@@ -0,0 +1,76 @@ 
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/timer/allwinner,sun4i-a10-timer.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Allwinner A10 Timer Device Tree Bindings
+
+maintainers:
+  - Chen-Yu Tsai <wens@csie.org>
+  - Maxime Ripard <maxime.ripard@bootlin.com>
+
+properties:
+  compatible:
+    enum:
+      - allwinner,sun4i-a10-timer
+      - allwinner,suniv-f1c100s-timer
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    description:
+      List of timers interrupts
+
+  clocks:
+    maxItems: 1
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          items:
+            const: allwinner,sun4i-a10-timer
+
+    then:
+      properties:
+        interrupts:
+          minItems: 6
+          maxItems: 6
+
+  - if:
+      properties:
+        compatible:
+          items:
+            const: allwinner,suniv-f1c100s-timer
+
+    then:
+      properties:
+        interrupts:
+          minItems: 3
+          maxItems: 3
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+
+additionalProperties: false
+
+examples:
+  - |
+    timer {
+        compatible = "allwinner,sun4i-a10-timer";
+        reg = <0x01c20c00 0x400>;
+        interrupts = <22>,
+                     <23>,
+                     <24>,
+                     <25>,
+                     <67>,
+                     <68>;
+        clocks = <&osc>;
+    };
+
+...
diff --git a/Documentation/devicetree/bindings/timer/allwinner,sun4i-timer.txt b/Documentation/devicetree/bindings/timer/allwinner,sun4i-timer.txt
deleted file mode 100644
index 3da9d515c03a..000000000000
--- a/Documentation/devicetree/bindings/timer/allwinner,sun4i-timer.txt
+++ /dev/null
@@ -1,19 +0,0 @@ 
-Allwinner A1X SoCs Timer Controller
-
-Required properties:
-
-- compatible : should be one of the following:
-              "allwinner,sun4i-a10-timer"
-              "allwinner,suniv-f1c100s-timer"
-- reg : Specifies base physical address and size of the registers.
-- interrupts : The interrupt of the first timer
-- clocks: phandle to the source clock (usually a 24 MHz fixed clock)
-
-Example:
-
-timer {
-	compatible = "allwinner,sun4i-a10-timer";
-	reg = <0x01c20c00 0x400>;
-	interrupts = <22>;
-	clocks = <&osc>;
-};