From patchwork Mon Sep 5 23:55:37 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Max Filippov X-Patchwork-Id: 113465 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 11AE9B6F7E for ; Tue, 6 Sep 2011 11:19:30 +1000 (EST) Received: from localhost ([::1]:45442 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1R0j24-0004DN-Ht for incoming@patchwork.ozlabs.org; Mon, 05 Sep 2011 19:56:52 -0400 Received: from eggs.gnu.org ([140.186.70.92]:36864) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1R0j1K-0003Cd-Dg for qemu-devel@nongnu.org; Mon, 05 Sep 2011 19:56:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1R0j1F-0003Iu-Va for qemu-devel@nongnu.org; Mon, 05 Sep 2011 19:56:05 -0400 Received: from [188.134.19.124] (port=53315 helo=octofox.metropolis) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1R0j1E-0003Hx-RV for qemu-devel@nongnu.org; Mon, 05 Sep 2011 19:56:01 -0400 Received: from octofox.metropolis (localhost [127.0.0.1]) by octofox.metropolis (8.14.5/8.14.5) with ESMTP id p85Nu9f4023064; Tue, 6 Sep 2011 03:56:09 +0400 Received: (from jcmvbkbc@localhost) by octofox.metropolis (8.14.5/8.14.5/Submit) id p85Nu9Uw023063; Tue, 6 Sep 2011 03:56:09 +0400 From: Max Filippov To: qemu-devel@nongnu.org Date: Tue, 6 Sep 2011 03:55:37 +0400 Message-Id: <1315266957-22979-14-git-send-email-jcmvbkbc@gmail.com> X-Mailer: git-send-email 1.7.6 In-Reply-To: <1315266957-22979-1-git-send-email-jcmvbkbc@gmail.com> References: <1315266957-22979-1-git-send-email-jcmvbkbc@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 188.134.19.124 Cc: jcmvbkbc@gmail.com Subject: [Qemu-devel] [PATCH v5 13/33] target-xtensa: mark reserved and TBD opcodes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Reserved opcodes must generate illegal instruction exception. Usually they signal emulation quality problems. Not implemented opcodes are good to see. Signed-off-by: Max Filippov --- target-xtensa/translate.c | 110 ++++++++++++++++++++++++++++++++++++++++++++- 1 files changed, 109 insertions(+), 1 deletions(-) diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c index dd89017..8f92dfb 100644 --- a/target-xtensa/translate.c +++ b/target-xtensa/translate.c @@ -267,6 +267,14 @@ static void disas_xtensa_insn(DisasContext *dc) } \ } while (0) +#define TBD() qemu_log("TBD(pc = %08x): %s:%d\n", dc->pc, __FILE__, __LINE__) +#define RESERVED() do { \ + qemu_log("RESERVED(pc = %08x, %02x%02x%02x): %s:%d\n", \ + dc->pc, b0, b1, b2, __FILE__, __LINE__); \ + goto invalid_opcode; \ + } while (0) + + #ifdef TARGET_WORDS_BIGENDIAN #define OP0 (((b0) & 0xf0) >> 4) #define OP1 (((b2) & 0xf0) >> 4) @@ -367,9 +375,11 @@ static void disas_xtensa_insn(DisasContext *dc) case 0: /*SNM0*/ switch (CALLX_M) { case 0: /*ILL*/ + TBD(); break; case 1: /*reserved*/ + RESERVED(); break; case 2: /*JR*/ @@ -381,9 +391,11 @@ static void disas_xtensa_insn(DisasContext *dc) case 1: /*RETWw*/ HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); + TBD(); break; case 3: /*reserved*/ + RESERVED(); break; } break; @@ -404,6 +416,7 @@ static void disas_xtensa_insn(DisasContext *dc) case 2: /*CALLX8w*/ case 3: /*CALLX12w*/ HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); + TBD(); break; } break; @@ -412,12 +425,59 @@ static void disas_xtensa_insn(DisasContext *dc) case 1: /*MOVSPw*/ HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); + TBD(); break; case 2: /*SYNC*/ + TBD(); + break; + + case 3: /*RFEIx*/ + TBD(); + break; + + case 4: /*BREAKx*/ + HAS_OPTION(XTENSA_OPTION_EXCEPTION); + TBD(); + break; + + case 5: /*SYSCALLx*/ + HAS_OPTION(XTENSA_OPTION_EXCEPTION); + TBD(); + break; + + case 6: /*RSILx*/ + HAS_OPTION(XTENSA_OPTION_INTERRUPT); + TBD(); + break; + + case 7: /*WAITIx*/ + HAS_OPTION(XTENSA_OPTION_INTERRUPT); + TBD(); + break; + + case 8: /*ANY4p*/ + HAS_OPTION(XTENSA_OPTION_BOOLEAN); + TBD(); + break; + + case 9: /*ALL4p*/ + HAS_OPTION(XTENSA_OPTION_BOOLEAN); + TBD(); break; - case 3: + case 10: /*ANY8p*/ + HAS_OPTION(XTENSA_OPTION_BOOLEAN); + TBD(); + break; + + case 11: /*ALL8p*/ + HAS_OPTION(XTENSA_OPTION_BOOLEAN); + TBD(); + break; + + default: /*reserved*/ + RESERVED(); break; } @@ -473,13 +533,16 @@ static void disas_xtensa_insn(DisasContext *dc) break; case 6: /*RER*/ + TBD(); break; case 7: /*WER*/ + TBD(); break; case 8: /*ROTWw*/ HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); + TBD(); break; case 14: /*NSAu*/ @@ -493,11 +556,13 @@ static void disas_xtensa_insn(DisasContext *dc) break; default: /*reserved*/ + RESERVED(); break; } break; case 5: /*TLB*/ + TBD(); break; case 6: /*RT0*/ @@ -518,11 +583,13 @@ static void disas_xtensa_insn(DisasContext *dc) break; default: /*reserved*/ + RESERVED(); break; } break; case 7: /*reserved*/ + RESERVED(); break; case 8: /*ADD*/ @@ -582,6 +649,9 @@ static void disas_xtensa_insn(DisasContext *dc) gen_rsr(dc, cpu_R[RRR_T], RSR_SR); gen_wsr(dc, RSR_SR, tmp); tcg_temp_free(tmp); + if (!sregnames[RSR_SR]) { + TBD(); + } } break; @@ -671,21 +741,29 @@ static void disas_xtensa_insn(DisasContext *dc) break; default: /*reserved*/ + RESERVED(); break; } break; case 2: /*RST2*/ + TBD(); break; case 3: /*RST3*/ switch (OP2) { case 0: /*RSR*/ gen_rsr(dc, cpu_R[RRR_T], RSR_SR); + if (!sregnames[RSR_SR]) { + TBD(); + } break; case 1: /*WSR*/ gen_wsr(dc, RSR_SR, cpu_R[RRR_T]); + if (!sregnames[RSR_SR]) { + TBD(); + } break; case 2: /*SEXTu*/ @@ -778,10 +856,12 @@ static void disas_xtensa_insn(DisasContext *dc) case 12: /*MOVFp*/ HAS_OPTION(XTENSA_OPTION_BOOLEAN); + TBD(); break; case 13: /*MOVTp*/ HAS_OPTION(XTENSA_OPTION_BOOLEAN); + TBD(); break; case 14: /*RUR*/ @@ -791,6 +871,7 @@ static void disas_xtensa_insn(DisasContext *dc) tcg_gen_mov_i32(cpu_R[RRR_R], cpu_UR[st]); } else { qemu_log("RUR %d not implemented, ", st); + TBD(); } } break; @@ -801,6 +882,7 @@ static void disas_xtensa_insn(DisasContext *dc) tcg_gen_mov_i32(cpu_UR[RSR_SR], cpu_R[RRR_T]); } else { qemu_log("WUR %d not implemented, ", RSR_SR); + TBD(); } } break; @@ -822,27 +904,34 @@ static void disas_xtensa_insn(DisasContext *dc) break; case 6: /*CUST0*/ + RESERVED(); break; case 7: /*CUST1*/ + RESERVED(); break; case 8: /*LSCXp*/ HAS_OPTION(XTENSA_OPTION_COPROCESSOR); + TBD(); break; case 9: /*LSC4*/ + TBD(); break; case 10: /*FP0*/ HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR); + TBD(); break; case 11: /*FP1*/ HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR); + TBD(); break; default: /*reserved*/ + RESERVED(); break; } break; @@ -894,6 +983,7 @@ static void disas_xtensa_insn(DisasContext *dc) break; case 7: /*CACHEc*/ + TBD(); break; case 9: /*L16SI*/ @@ -946,6 +1036,7 @@ static void disas_xtensa_insn(DisasContext *dc) break; default: /*reserved*/ + RESERVED(); break; } break; @@ -953,10 +1044,12 @@ static void disas_xtensa_insn(DisasContext *dc) case 3: /*LSCIp*/ HAS_OPTION(XTENSA_OPTION_COPROCESSOR); + TBD(); break; case 4: /*MAC16d*/ HAS_OPTION(XTENSA_OPTION_MAC16); + TBD(); break; case 5: /*CALLN*/ @@ -970,6 +1063,7 @@ static void disas_xtensa_insn(DisasContext *dc) case 2: /*CALL8w*/ case 3: /*CALL12w*/ HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); + TBD(); break; } break; @@ -1012,28 +1106,35 @@ static void disas_xtensa_insn(DisasContext *dc) switch (BRI8_M) { case 0: /*ENTRYw*/ HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); + TBD(); break; case 1: /*B1*/ switch (BRI8_R) { case 0: /*BFp*/ HAS_OPTION(XTENSA_OPTION_BOOLEAN); + TBD(); break; case 1: /*BTp*/ HAS_OPTION(XTENSA_OPTION_BOOLEAN); + TBD(); break; case 8: /*LOOP*/ + TBD(); break; case 9: /*LOOPNEZ*/ + TBD(); break; case 10: /*LOOPGTZ*/ + TBD(); break; default: /*reserved*/ + RESERVED(); break; } @@ -1169,28 +1270,35 @@ static void disas_xtensa_insn(DisasContext *dc) break; case 1: /*RETW.Nn*/ + HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); + TBD(); break; case 2: /*BREAK.Nn*/ + TBD(); break; case 3: /*NOP.Nn*/ break; case 6: /*ILL.Nn*/ + TBD(); break; default: /*reserved*/ + RESERVED(); break; } break; default: /*reserved*/ + RESERVED(); break; } break; default: /*reserved*/ + RESERVED(); break; }