From patchwork Mon Sep 5 23:55:42 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Max Filippov X-Patchwork-Id: 113457 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id EBBCDB6F7E for ; Tue, 6 Sep 2011 10:53:01 +1000 (EST) Received: from localhost ([::1]:45528 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1R0j2L-0004nh-4d for incoming@patchwork.ozlabs.org; Mon, 05 Sep 2011 19:57:09 -0400 Received: from eggs.gnu.org ([140.186.70.92]:54366) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1R0j1U-0003fS-9U for qemu-devel@nongnu.org; Mon, 05 Sep 2011 19:56:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1R0j1I-0003Js-LZ for qemu-devel@nongnu.org; Mon, 05 Sep 2011 19:56:11 -0400 Received: from [188.134.19.124] (port=53331 helo=octofox.metropolis) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1R0j1H-0003J0-Ak for qemu-devel@nongnu.org; Mon, 05 Sep 2011 19:56:03 -0400 Received: from octofox.metropolis (localhost [127.0.0.1]) by octofox.metropolis (8.14.5/8.14.5) with ESMTP id p85NuBsw023084; Tue, 6 Sep 2011 03:56:11 +0400 Received: (from jcmvbkbc@localhost) by octofox.metropolis (8.14.5/8.14.5/Submit) id p85NuBL8023083; Tue, 6 Sep 2011 03:56:11 +0400 From: Max Filippov To: qemu-devel@nongnu.org Date: Tue, 6 Sep 2011 03:55:42 +0400 Message-Id: <1315266957-22979-19-git-send-email-jcmvbkbc@gmail.com> X-Mailer: git-send-email 1.7.6 In-Reply-To: <1315266957-22979-1-git-send-email-jcmvbkbc@gmail.com> References: <1315266957-22979-1-git-send-email-jcmvbkbc@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 188.134.19.124 Cc: jcmvbkbc@gmail.com Subject: [Qemu-devel] [PATCH v5 18/33] target-xtensa: implement RST2 group (32 bit mul/div/rem) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Max Filippov --- target-xtensa/translate.c | 77 ++++++++++++++++++++++++++++++++++++++++++++- 1 files changed, 76 insertions(+), 1 deletions(-) diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c index dccd453..bc04a10 100644 --- a/target-xtensa/translate.c +++ b/target-xtensa/translate.c @@ -878,7 +878,82 @@ static void disas_xtensa_insn(DisasContext *dc) break; case 2: /*RST2*/ - TBD(); + if (OP2 >= 12) { + HAS_OPTION(XTENSA_OPTION_32_BIT_IDIV); + int label = gen_new_label(); + tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_T], 0, label); + gen_exception_cause(dc, INTEGER_DIVIDE_BY_ZERO_CAUSE); + gen_set_label(label); + } + + switch (OP2) { + case 8: /*MULLi*/ + HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL); + tcg_gen_mul_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]); + break; + + case 10: /*MULUHi*/ + case 11: /*MULSHi*/ + HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL); + { + TCGv_i64 r = tcg_temp_new_i64(); + TCGv_i64 s = tcg_temp_new_i64(); + TCGv_i64 t = tcg_temp_new_i64(); + + if (OP2 == 10) { + tcg_gen_extu_i32_i64(s, cpu_R[RRR_S]); + tcg_gen_extu_i32_i64(t, cpu_R[RRR_T]); + } else { + tcg_gen_ext_i32_i64(s, cpu_R[RRR_S]); + tcg_gen_ext_i32_i64(t, cpu_R[RRR_T]); + } + tcg_gen_mul_i64(r, s, t); + tcg_gen_shri_i64(r, r, 32); + tcg_gen_trunc_i64_i32(cpu_R[RRR_R], r); + + tcg_temp_free_i64(r); + tcg_temp_free_i64(s); + tcg_temp_free_i64(t); + } + break; + + case 12: /*QUOUi*/ + tcg_gen_divu_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]); + break; + + case 13: /*QUOSi*/ + case 15: /*REMSi*/ + { + int label1 = gen_new_label(); + int label2 = gen_new_label(); + + tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_S], 0x80000000, + label1); + tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_T], 0xffffffff, + label1); + tcg_gen_movi_i32(cpu_R[RRR_R], + OP2 == 13 ? 0x80000000 : 0); + tcg_gen_br(label2); + gen_set_label(label1); + if (OP2 == 13) { + tcg_gen_div_i32(cpu_R[RRR_R], + cpu_R[RRR_S], cpu_R[RRR_T]); + } else { + tcg_gen_rem_i32(cpu_R[RRR_R], + cpu_R[RRR_S], cpu_R[RRR_T]); + } + gen_set_label(label2); + } + break; + + case 14: /*REMUi*/ + tcg_gen_remu_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]); + break; + + default: /*reserved*/ + RESERVED(); + break; + } break; case 3: /*RST3*/