From patchwork Fri Jul 19 12:57:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrick DELAUNAY X-Patchwork-Id: 1134038 X-Patchwork-Delegate: patrick.delaunay73@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=st.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=st.com header.i=@st.com header.b="MQ6pUkLS"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 45qrhw5sc8z9s3l for ; Fri, 19 Jul 2019 23:00:48 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 8654CC21C6A; Fri, 19 Jul 2019 13:00:36 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 3CFA3C21D56; Fri, 19 Jul 2019 13:00:34 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 5F0CBC21DD9; Fri, 19 Jul 2019 13:00:21 +0000 (UTC) Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [62.209.51.94]) by lists.denx.de (Postfix) with ESMTPS id 5AA9EC21DEC for ; Fri, 19 Jul 2019 13:00:21 +0000 (UTC) Received: from pps.filterd (m0046037.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x6JD06bM021006; Fri, 19 Jul 2019 15:00:20 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=st.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=STMicroelectronics; bh=EiFIC7VsJq0k0pGRV7dMHm5LCB02FIcOXZs/yOOvucI=; b=MQ6pUkLSwD/H4S8ZA622aHPij5Oq6M9XeoUHp7/wxefbz5oJirJm9zHGgnkXLZoDX6PS zlqIZpA2B7dh+9WcRJQ7IAeBKBZ++GuY9m+vJUT1XyXRFaH/BB/HuffI9F1dWkOdnH58 qXLPfI/Dle05Xqro2MTeVqUH7S26yTqtcq4rt3dsACI84jkmGLlfRRvU/cewcXHhHlTs ZT1cMCBrQ6o3Y4xg+5ZqxzHm+ElJqPOJ6HAMUZcaJDnP8C+RyrbwMY4LlGWvPFcYwED9 SVaWVczw+JEdw7I5Z/QxWJb+d9ES0ZcrgHngcBmRh2ZFMcjVIFAC3WTWJC2yACEi7KR1 /A== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 2tsdepv66k-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Fri, 19 Jul 2019 15:00:20 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 58A8172; Fri, 19 Jul 2019 12:57:46 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas21.st.com [10.75.90.44]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 44E032D53; Fri, 19 Jul 2019 12:57:46 +0000 (GMT) Received: from SAFEX1HUBCAS23.st.com (10.75.90.47) by SAFEX1HUBCAS21.st.com (10.75.90.44) with Microsoft SMTP Server (TLS) id 14.3.439.0; Fri, 19 Jul 2019 14:57:46 +0200 Received: from localhost (10.201.23.85) by webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.439.0; Fri, 19 Jul 2019 14:57:46 +0200 From: Patrick Delaunay To: Date: Fri, 19 Jul 2019 14:57:26 +0200 Message-ID: <1563541046-6432-15-git-send-email-patrick.delaunay@st.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1563541046-6432-1-git-send-email-patrick.delaunay@st.com> References: <1563541046-6432-1-git-send-email-patrick.delaunay@st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.23.85] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-07-19_09:, , signatures=0 Cc: U-Boot STM32 Subject: [U-Boot] [RFC PATCH 14/14] stm32mp1: add support for virtual partition read X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add read for OTP and PMIC NVM with alternates on virtual DFU device. Signed-off-by: Patrick Delaunay # Conflicts: # board/st/stm32mp1/stm32mp1.c --- board/st/stm32mp1/stm32mp1.c | 83 +++++++++++++++++++++++++++++++++++++ configs/stm32mp15_basic_defconfig | 1 + configs/stm32mp15_trusted_defconfig | 1 + 3 files changed, 85 insertions(+) diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c index 68bd06c..4d5cd70 100644 --- a/board/st/stm32mp1/stm32mp1.c +++ b/board/st/stm32mp1/stm32mp1.c @@ -819,7 +819,90 @@ void set_dfu_alt_info(char *interface, char *devstr) if (!IS_ERR_OR_NULL(mtd)) board_get_alt_info("spi-nand0", buf); +#ifdef CONFIG_DFU_VIRT + strncat(buf, "&virt 0=OTP", DFU_ALT_BUF_LEN); + + if (IS_ENABLED(CONFIG_PMIC_STPMIC1)) + strncat(buf, "&virt 1=PMIC", DFU_ALT_BUF_LEN); +#endif + env_set("dfu_alt_info", buf); puts("DFU alt info setting: done\n"); } + +#if CONFIG_IS_ENABLED(DFU_VIRT) +#include +#include + +int dfu_otp_read(u64 offset, u8 *buffer, long *size) +{ + struct udevice *dev; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_GET_DRIVER(stm32mp_bsec), + &dev); + if (ret) + return ret; + + ret = misc_read(dev, offset + STM32_BSEC_OTP_OFFSET, buffer, *size); + if (ret >= 0) { + *size = ret; + ret = 0; + } + + return 0; +} + +int dfu_pmic_read(u64 offset, u8 *buffer, long *size) +{ + int ret; +#ifdef CONFIG_PMIC_STPMIC1 + struct udevice *dev; + + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_GET_DRIVER(stpmic1_nvm), + &dev); + if (ret) + return ret; + + ret = misc_read(dev, 0xF8 + offset, buffer, *size); + if (ret >= 0) { + *size = ret; + ret = 0; + } + if (ret == -EACCES) { + *size = 0; + ret = 0; + } +#else + pr_err("PMIC update not supported"); + ret = -EOPNOTSUPP; +#endif + + return ret; +} + +int dfu_read_medium_virt(struct dfu_entity *dfu, u64 offset, + void *buf, long *len) +{ + switch (dfu->data.virt.dev_num) { + case 0x0: + return dfu_otp_read(offset, buf, len); + case 0x1: + return dfu_pmic_read(offset, buf, len); + } + *len = 0; + return 0; +} + +int __weak dfu_get_medium_size_virt(struct dfu_entity *dfu, u64 *size) +{ + *size = SZ_1K; + + return 0; +} + +#endif + #endif diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig index 4728376..ba7b2f6 100644 --- a/configs/stm32mp15_basic_defconfig +++ b/configs/stm32mp15_basic_defconfig @@ -57,6 +57,7 @@ CONFIG_STM32_ADC=y CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_DFU_MTD=y +CONFIG_DFU_VIRT=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0xC0000000 CONFIG_FASTBOOT_BUF_SIZE=0x02000000 diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig index 0d9e13e..25d9e4f 100644 --- a/configs/stm32mp15_trusted_defconfig +++ b/configs/stm32mp15_trusted_defconfig @@ -49,6 +49,7 @@ CONFIG_STM32_ADC=y CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_DFU_MTD=y +CONFIG_DFU_VIRT=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0xC0000000 CONFIG_FASTBOOT_BUF_SIZE=0x02000000