From patchwork Fri Nov 28 19:51:23 2008 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnd Bergmann X-Patchwork-Id: 11339 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from ozlabs.org (localhost [127.0.0.1]) by ozlabs.org (Postfix) with ESMTP id 7A8C947516 for ; Sat, 29 Nov 2008 07:13:24 +1100 (EST) X-Original-To: cbe-oss-dev@ozlabs.org Delivered-To: cbe-oss-dev@ozlabs.org Received: from mout-xforward.kundenserver.de (mout-xforward.kundenserver.de [212.227.17.4]) by ozlabs.org (Postfix) with ESMTP id 560A2DDDDF; Sat, 29 Nov 2008 07:12:31 +1100 (EST) Received: from dyn-9-152-222-92.boeblingen.de.ibm.com (blueice1n1.de.ibm.com [195.212.29.163]) by mrelayeu.kundenserver.de (node=mrelayeu5) with ESMTP (Nemesis) id 0ML25U-1L69hU40ic-0003HI; Fri, 28 Nov 2008 21:12:29 +0100 Message-Id: <20081128200325.075254354@arndb.de> References: <20081128195120.869318403@arndb.de> User-Agent: quilt/0.46-1 Date: Fri, 28 Nov 2008 20:51:23 +0100 From: Arnd Bergmann To: linuxppc-dev@ozlabs.org Content-Disposition: inline; filename=0003-powerpc-mpic-don-t-reset-affinity-for-secondary-MPI.patch X-Provags-ID: V01U2FsdGVkX1+GupV4u3hi0EQdv/TfmGVXJA/1OPIFD8JCO1h oM3gvXdMDJ4MA6hW4O7YdPoirHDWgWnmgiO1iUEZCjJvNCqMW0 SBuwxvcVsvD3BOLUdp6hg== Cc: cbe-oss-dev@ozlabs.org Subject: [Cbe-oss-dev] [patch 3/4] powerpc/mpic: dont reset affinity for secondary MPIC on boot X-BeenThere: cbe-oss-dev@ozlabs.org X-Mailman-Version: 2.1.11 Precedence: list List-Id: Discussion about Open Source Software for the Cell Broadband Engine List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: cbe-oss-dev-bounces+patchwork-incoming=ozlabs.org@ozlabs.org Errors-To: cbe-oss-dev-bounces+patchwork-incoming=ozlabs.org@ozlabs.org Kexec/kdump currently fails on the IBM QS2x blades when the kexec happens on a CPU other than the initial boot CPU. It turns out that this is the result of mpic_init trying to set affinity of each interrupt vector to the current boot CPU. As far as I can tell, the same problem is likely to exist on any secondary MPIC, because they have to deliver interrupts to the first output all the time. There are two potential solutions for this: either not set up affinity at all for secondary MPICs, or assume that a single CPU output is connected to the upstream interrupt controller and hardcode affinity to that per architecture. This patch implements the second approach, defaulting to the first output. Currently, all known secondary MPICs are routed to their upstream port using the first destination, so we hardcode that. Signed-off-by: Arnd Bergmann Acked-by: Benjamin Herrenschmidt --- arch/powerpc/sysdev/mpic.c | 9 +++++++-- 1 files changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c index f6299cc..b24e1d0 100644 --- a/arch/powerpc/sysdev/mpic.c +++ b/arch/powerpc/sysdev/mpic.c @@ -1271,6 +1271,7 @@ void __init mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count) void __init mpic_init(struct mpic *mpic) { int i; + int cpu; BUG_ON(mpic->num_sources == 0); @@ -1313,6 +1314,11 @@ void __init mpic_init(struct mpic *mpic) mpic_pasemi_msi_init(mpic); + if (mpic->flags & MPIC_PRIMARY) + cpu = hard_smp_processor_id(); + else + cpu = 0; + for (i = 0; i < mpic->num_sources; i++) { /* start with vector = source number, and masked */ u32 vecpri = MPIC_VECPRI_MASK | i | @@ -1323,8 +1329,7 @@ void __init mpic_init(struct mpic *mpic) continue; /* init hw */ mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri); - mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), - 1 << hard_smp_processor_id()); + mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1 << cpu); } /* Init spurious vector */