From patchwork Thu Jul 18 18:04:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabio Estevam X-Patchwork-Id: 1133800 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="SBSKtoQ/"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 45qMVF5glhz9s3l for ; Fri, 19 Jul 2019 04:04:51 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 721C1C21FE1; Thu, 18 Jul 2019 18:04:43 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 4A032C21F75; Thu, 18 Jul 2019 18:04:41 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id C25B6C21F3F; Thu, 18 Jul 2019 18:04:39 +0000 (UTC) Received: from mail-qt1-f194.google.com (mail-qt1-f194.google.com [209.85.160.194]) by lists.denx.de (Postfix) with ESMTPS id 362FCC21F01 for ; Thu, 18 Jul 2019 18:04:39 +0000 (UTC) Received: by mail-qt1-f194.google.com with SMTP id x22so23264111qtp.12 for ; Thu, 18 Jul 2019 11:04:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=JMimpcOEsyRWnDqjVpcr9oXmtTyZdhfCpYyeP7dvKos=; b=SBSKtoQ/1MFOfkQhN4NjZ6l6913s2/BJ/96Ux5aaV6CAWAdEqLD+NaEu3xQegGcJiM MfjYwlyJxO4Db1jqvdYO+aIPTsclhvIfHU0aCNDh4kb3vBYYF8HnDjNCg/VoNN9ZHGtu OfyiGv9T7WNlW6lKvqcnYoIorjDRnU/n9XWjFppOVtL73pSlWH2GM1GUs7+V6IinZ3tE LvM1xFRk0Zq8U5Y6Nr4SvsuRSdp3gEkVqIE5NL4Mm49qVTvSi7zPyRi2JFT8FcCQO4pc dGRk4fYvo74XotbNy5v4Svecu6kXbYfRb1zuNtqco4qR1d1OZZRf3a/pTDlsux2qfniT 0MOQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=JMimpcOEsyRWnDqjVpcr9oXmtTyZdhfCpYyeP7dvKos=; b=Q1KBTwYF8smV6IJe5aM9ldGZulLwANrm2GR6gFjhNDnIm6GNo8blMAKezwlrjQ8WT+ g2UoGhz+tQ18Y6KcOUcx2gDnnI9g2MH/+yyNOFP9WA6X++IYtr7mi7KSeFVhkwJlJdBN cy4mMHd7J6zX+yA/bd/jxYrK7ZD4ObvKGvOt9amPg/A6XsfDZA05cM1Na4kkYz9sGwDD WuWBbVL8pYqC6r6OPYCs2aDlleeB/ob1TXNLMhcHOgTntjQ7Lg2fvd+K9ilB+7E1vNrd ojUkLw/xHfckVw4gFQZMWJneuonqpwdcsw/rZd9gZOxyf5beGUsmknmF+NMqgSvCjy3r COxg== X-Gm-Message-State: APjAAAUkek9ITASdL02cWj8TjExKfnOEdlHhhsEYnh/DFSmPYopDZnB9 xPpuXhY69OkeB/chi++W5Qs= X-Google-Smtp-Source: APXvYqxKDmfyJtnh1X5haZPL/YWekIpLCoH0LZpzK+6/VGIKfp0D8GSDgK/ChA7J25th4vbtgqwrxw== X-Received: by 2002:ad4:4a92:: with SMTP id h18mr33885838qvx.235.1563473077726; Thu, 18 Jul 2019 11:04:37 -0700 (PDT) Received: from fabio-Latitude-E5450.am.freescale.net ([2804:14c:482:3c8:56cb:1049:60d2:137b]) by smtp.gmail.com with ESMTPSA id y194sm13876737qkb.111.2019.07.18.11.04.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 18 Jul 2019 11:04:37 -0700 (PDT) From: Fabio Estevam To: sbabic@denx.de Date: Thu, 18 Jul 2019 15:04:22 -0300 Message-Id: <20190718180425.29472-1-festevam@gmail.com> X-Mailer: git-send-email 2.17.1 Cc: u-boot@lists.denx.de, uboot-imx@nxp.com Subject: [U-Boot] [PATCH 1/4] imx: Place imx_ddr_size() into a separate file X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Place imx_ddr_size() into a separate file. The motivation for doing this is to be able to easily reuse imx_ddr_size() on i.MX7ULP. Currently imx_ddr_size() is inside arch/arm/mach-imx/cpu.c, which is not built for i.MX7ULP. Changing the logic to allow building cpu.c for i.MX7UP would require adding several ifdef's, leading to a not a very elegant solution. To allow better reuse, just place imx_ddr_size() into a common mmdc_size.c file. Signed-off-by: Fabio Estevam --- arch/arm/mach-imx/Makefile | 2 +- arch/arm/mach-imx/cpu.c | 53 --------------------------------- arch/arm/mach-imx/mmdc_size.c | 55 +++++++++++++++++++++++++++++++++++ 3 files changed, 56 insertions(+), 54 deletions(-) create mode 100644 arch/arm/mach-imx/mmdc_size.c diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 898478fc4a..0c8519be94 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -20,7 +20,7 @@ obj-y += cpu.o endif ifeq ($(SOC),$(filter $(SOC),mx5 mx6)) -obj-y += cpu.o speed.o +obj-y += cpu.o speed.o mmdc_size.o obj-$(CONFIG_GPT_TIMER) += timer.o obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o endif diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c index 3a8cf30c06..0b30ff40cd 100644 --- a/arch/arm/mach-imx/cpu.c +++ b/arch/arm/mach-imx/cpu.c @@ -87,59 +87,6 @@ static char *get_reset_cause(void) } #endif -#if defined(CONFIG_MX53) || defined(CONFIG_MX6) -#if defined(CONFIG_MX53) -#define MEMCTL_BASE ESDCTL_BASE_ADDR -#else -#define MEMCTL_BASE MMDC_P0_BASE_ADDR -#endif -static const unsigned char col_lookup[] = {9, 10, 11, 8, 12, 9, 9, 9}; -static const unsigned char bank_lookup[] = {3, 2}; - -/* these MMDC registers are common to the IMX53 and IMX6 */ -struct esd_mmdc_regs { - uint32_t ctl; - uint32_t pdc; - uint32_t otc; - uint32_t cfg0; - uint32_t cfg1; - uint32_t cfg2; - uint32_t misc; -}; - -#define ESD_MMDC_CTL_GET_ROW(mdctl) ((ctl >> 24) & 7) -#define ESD_MMDC_CTL_GET_COLUMN(mdctl) ((ctl >> 20) & 7) -#define ESD_MMDC_CTL_GET_WIDTH(mdctl) ((ctl >> 16) & 3) -#define ESD_MMDC_CTL_GET_CS1(mdctl) ((ctl >> 30) & 1) -#define ESD_MMDC_MISC_GET_BANK(mdmisc) ((misc >> 5) & 1) - -/* - * imx_ddr_size - return size in bytes of DRAM according MMDC config - * The MMDC MDCTL register holds the number of bits for row, col, and data - * width and the MMDC MDMISC register holds the number of banks. Combine - * all these bits to determine the meme size the MMDC has been configured for - */ -unsigned imx_ddr_size(void) -{ - struct esd_mmdc_regs *mem = (struct esd_mmdc_regs *)MEMCTL_BASE; - unsigned ctl = readl(&mem->ctl); - unsigned misc = readl(&mem->misc); - int bits = 11 + 0 + 0 + 1; /* row + col + bank + width */ - - bits += ESD_MMDC_CTL_GET_ROW(ctl); - bits += col_lookup[ESD_MMDC_CTL_GET_COLUMN(ctl)]; - bits += bank_lookup[ESD_MMDC_MISC_GET_BANK(misc)]; - bits += ESD_MMDC_CTL_GET_WIDTH(ctl); - bits += ESD_MMDC_CTL_GET_CS1(ctl); - - /* The MX6 can do only 3840 MiB of DRAM */ - if (bits == 32) - return 0xf0000000; - - return 1 << bits; -} -#endif - #if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD) const char *get_imx_type(u32 imxtype) diff --git a/arch/arm/mach-imx/mmdc_size.c b/arch/arm/mach-imx/mmdc_size.c new file mode 100644 index 0000000000..8a3c6bdea6 --- /dev/null +++ b/arch/arm/mach-imx/mmdc_size.c @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include +#include + +#if defined(CONFIG_MX53) +#define MEMCTL_BASE ESDCTL_BASE_ADDR +#else +#define MEMCTL_BASE MMDC_P0_BASE_ADDR +#endif +static const unsigned char col_lookup[] = {9, 10, 11, 8, 12, 9, 9, 9}; +static const unsigned char bank_lookup[] = {3, 2}; + +/* these MMDC registers are common to the IMX53 and IMX6 */ +struct esd_mmdc_regs { + uint32_t ctl; + uint32_t pdc; + uint32_t otc; + uint32_t cfg0; + uint32_t cfg1; + uint32_t cfg2; + uint32_t misc; +}; + +#define ESD_MMDC_CTL_GET_ROW(mdctl) ((ctl >> 24) & 7) +#define ESD_MMDC_CTL_GET_COLUMN(mdctl) ((ctl >> 20) & 7) +#define ESD_MMDC_CTL_GET_WIDTH(mdctl) ((ctl >> 16) & 3) +#define ESD_MMDC_CTL_GET_CS1(mdctl) ((ctl >> 30) & 1) +#define ESD_MMDC_MISC_GET_BANK(mdmisc) ((misc >> 5) & 1) + +/* + * imx_ddr_size - return size in bytes of DRAM according MMDC config + * The MMDC MDCTL register holds the number of bits for row, col, and data + * width and the MMDC MDMISC register holds the number of banks. Combine + * all these bits to determine the meme size the MMDC has been configured for + */ +unsigned imx_ddr_size(void) +{ + struct esd_mmdc_regs *mem = (struct esd_mmdc_regs *)MEMCTL_BASE; + unsigned ctl = readl(&mem->ctl); + unsigned misc = readl(&mem->misc); + int bits = 11 + 0 + 0 + 1; /* row + col + bank + width */ + + bits += ESD_MMDC_CTL_GET_ROW(ctl); + bits += col_lookup[ESD_MMDC_CTL_GET_COLUMN(ctl)]; + bits += bank_lookup[ESD_MMDC_MISC_GET_BANK(misc)]; + bits += ESD_MMDC_CTL_GET_WIDTH(ctl); + bits += ESD_MMDC_CTL_GET_CS1(ctl); + + /* The MX6 can do only 3840 MiB of DRAM */ + if (bits == 32) + return 0xf0000000; + + return 1 << bits; +}