[U-Boot,26/50] doc: board: Add Google Chromebook Link board doc
diff mbox series

Message ID 1563435275-22326-27-git-send-email-bmeng.cn@gmail.com
State Accepted
Commit c9bfc02a4a9a9649a36793309bc54f9751dffb12
Delegated to: Tom Rini
Headers show
Series
  • doc: Shape into useful HTML docs
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Commit Message

Bin Meng July 18, 2019, 7:34 a.m. UTC
This extracts Google Chromebook Link board specific information from
README.x86, converts plain text documentation to reST format and
adds it to Sphinx TOC tree. No essential content change.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

 doc/README.x86                       | 31 -------------------------------
 doc/board/google/chromebook_link.rst | 34 ++++++++++++++++++++++++++++++++++
 doc/board/google/index.rst           |  9 +++++++++
 doc/board/index.rst                  |  1 +
 4 files changed, 44 insertions(+), 31 deletions(-)
 create mode 100644 doc/board/google/chromebook_link.rst
 create mode 100644 doc/board/google/index.rst

Patch
diff mbox series

diff --git a/doc/README.x86 b/doc/README.x86
index e72f840..a8ad956 100644
--- a/doc/README.x86
+++ b/doc/README.x86
@@ -65,37 +65,6 @@  Both tell the Makefile to build u-boot.rom as a target.
 
 ---
 
-Chromebook Link specific instructions for bare mode:
-
-First, you need the following binary blobs:
-
-* descriptor.bin - Intel flash descriptor
-* me.bin - Intel Management Engine
-* mrc.bin - Memory Reference Code, which sets up SDRAM
-* video ROM - sets up the display
-
-You can get these binary blobs by:
-
-$ git clone http://review.coreboot.org/p/blobs.git
-$ cd blobs
-
-Find the following files:
-
-* ./mainboard/google/link/descriptor.bin
-* ./mainboard/google/link/me.bin
-* ./northbridge/intel/sandybridge/systemagent-r6.bin
-
-The 3rd one should be renamed to mrc.bin.
-As for the video ROM, you can get it here [3] and rename it to vga.bin.
-Make sure all these binary blobs are put in the board directory.
-
-Now you can build U-Boot and obtain u-boot.rom:
-
-$ make chromebook_link_defconfig
-$ make all
-
----
-
 Chromebook Samus (2015 Pixel) instructions for bare mode:
 
 First, you need the following binary blobs:
diff --git a/doc/board/google/chromebook_link.rst b/doc/board/google/chromebook_link.rst
new file mode 100644
index 0000000..1608030
--- /dev/null
+++ b/doc/board/google/chromebook_link.rst
@@ -0,0 +1,34 @@ 
+.. SPDX-License-Identifier: GPL-2.0+
+.. sectionauthor:: Simon Glass <sjg@chromium.org>
+
+Chromebook Link
+===============
+
+First, you need the following binary blobs:
+
+   * descriptor.bin - Intel flash descriptor
+   * me.bin - Intel Management Engine
+   * mrc.bin - Memory Reference Code, which sets up SDRAM
+   * video ROM - sets up the display
+
+You can get these binary blobs by::
+
+   $ git clone http://review.coreboot.org/p/blobs.git
+   $ cd blobs
+
+Find the following files:
+
+   * ./mainboard/google/link/descriptor.bin
+   * ./mainboard/google/link/me.bin
+   * ./northbridge/intel/sandybridge/systemagent-r6.bin
+
+The 3rd one should be renamed to mrc.bin.
+As for the video ROM, you can get it `here`_ and rename it to vga.bin.
+Make sure all these binary blobs are put in the board directory.
+
+Now you can build U-Boot and obtain u-boot.rom::
+
+   $ make chromebook_link_defconfig
+   $ make all
+
+.. _here: http://www.coreboot.org/~stepan/pci8086,0166.rom
diff --git a/doc/board/google/index.rst b/doc/board/google/index.rst
new file mode 100644
index 0000000..93833c5
--- /dev/null
+++ b/doc/board/google/index.rst
@@ -0,0 +1,9 @@ 
+.. SPDX-License-Identifier: GPL-2.0+
+
+Google
+======
+
+.. toctree::
+   :maxdepth: 2
+
+   chromebook_link
diff --git a/doc/board/index.rst b/doc/board/index.rst
index 99b5d2f..59f745d 100644
--- a/doc/board/index.rst
+++ b/doc/board/index.rst
@@ -6,4 +6,5 @@  Board-specific doc
 .. toctree::
    :maxdepth: 2
 
+   google/index
    intel/index