From patchwork Thu Jul 18 07:34:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1133603 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="S6k3AiGD"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 45q62F0Mxmz9s3l for ; Thu, 18 Jul 2019 17:58:11 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id A8761C21FD4; Thu, 18 Jul 2019 07:53:58 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 52FD3C22029; Thu, 18 Jul 2019 07:37:37 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id C7B3CC22006; Thu, 18 Jul 2019 07:35:38 +0000 (UTC) Received: from mail-pg1-f193.google.com (mail-pg1-f193.google.com [209.85.215.193]) by lists.denx.de (Postfix) with ESMTPS id F1140C21FA3 for ; Thu, 18 Jul 2019 07:35:33 +0000 (UTC) Received: by mail-pg1-f193.google.com with SMTP id x15so2129492pgg.8 for ; Thu, 18 Jul 2019 00:35:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=p3eX+V+4YY9IfFpqptJzRplD5c/cKLB8fDbuFbml1g0=; b=S6k3AiGDEBgmPMd30fHwpNYrZWYwFzmQ5ohJHN3xSkU0j+mWblLkvj3pvMB4G3PSno PalfRkA13E9rwWkKnp1cioGLGqUdi1LLbp0haeLis5Nkbck/SAaLiWtUGhcTji2zPh84 k2lpupsPzcQZPlbw4jJJvyrZA+sjawn0j6r27S3xTueDiLaN+itg5v0w4O1ZDTPn0wKh rM1+vmKeeVf1ZK0kTsiWXl3XOvbz1fO+Fg17zVQNjUfILIgLcJWpxAkh7RdEDDL+kb9r 8kPPKEQ+iVp1x0WS3t/XUuX2bNpKC9JyUjdWVEbBNPJ4+p947t5LZaOGeT7H17vlTvg9 STbw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=p3eX+V+4YY9IfFpqptJzRplD5c/cKLB8fDbuFbml1g0=; b=rgGuBTY19f9xNpBNJ5jJePs9fy5202T6cDZ3ybY57Ztud9mZoxTEK3vCd8arKrYqvn kTFPS8JmVHVdwwAyu+51CK7474aBCa3XokLMVDs86u80wicSaCnsnFBdmHyDgRUrpQph jQXzDhZH3Nv1yf9KZqiRIXU9NrAgJGQ+djPsLcSgM3UaI6wKy8gVQNMs/yfpUDV/NuKR 37TAoeFIEnGOlpf1o0dgiDo+aatCxmDD3NbA4qs1fB5PJvQwetCJGt+dczE4FE5E4Jo6 teJ/zV7pwYie5OsaszUT4kuwfW7a5h7jJA4fSz248BYdKeEqfbBqxD7Pj8FVTH1sAXab jF2g== X-Gm-Message-State: APjAAAUwoMVuCPAvvwuMbc2iC2atjoVCCtesXAZFjX7M2YHgk5lhcOq+ 5697BztCJaPhrPQ/yyOk8m4= X-Google-Smtp-Source: APXvYqzpJ5bK5Vy5N6N+K/AncocA1L34RjAgznBDl60TQScaCmN3sACFUj5BcUafhjD/6qkia0epKw== X-Received: by 2002:a63:2ec9:: with SMTP id u192mr45180058pgu.16.1563435329415; Thu, 18 Jul 2019 00:35:29 -0700 (PDT) Received: from localhost.localdomain (unknown-224-80.windriver.com. [147.11.224.80]) by smtp.gmail.com with ESMTPSA id q1sm39859821pfn.178.2019.07.18.00.35.28 (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 18 Jul 2019 00:35:28 -0700 (PDT) From: Bin Meng To: Tom Rini , Simon Glass , Wolfgang Denk , Heinrich Schuchardt , Mario Six , U-Boot Mailing List Date: Thu, 18 Jul 2019 00:34:28 -0700 Message-Id: <1563435275-22326-44-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1563435275-22326-1-git-send-email-bmeng.cn@gmail.com> References: <1563435275-22326-1-git-send-email-bmeng.cn@gmail.com> Subject: [U-Boot] [PATCH 43/50] doc: arch: Convert README.NDS32 to reST X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Convert plain text documentation to reStructuredText format and add it to Sphinx TOC tree. No essential content change. This also merges README.N1213 contents into the new nds32.rst file. Signed-off-by: Bin Meng --- doc/README.N1213 | 55 ----------------------------- doc/README.NDS32 | 41 ---------------------- doc/arch/index.rst | 1 + doc/arch/nds32.rst | 101 +++++++++++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 102 insertions(+), 96 deletions(-) delete mode 100644 doc/README.N1213 delete mode 100644 doc/README.NDS32 create mode 100644 doc/arch/nds32.rst diff --git a/doc/README.N1213 b/doc/README.N1213 deleted file mode 100644 index e107166..0000000 --- a/doc/README.N1213 +++ /dev/null @@ -1,55 +0,0 @@ -N1213 is a configurable hard/soft core of NDS32's N12 CPU family. - -Features -======== - -CPU Core - - 16-/32-bit mixable instruction format. - - 32 general-purpose 32-bit registers. - - 8-stage pipeline. - - Dynamic branch prediction. - - 32/64/128/256 BTB. - - Return address stack (RAS). - - Vector interrupts for internal/external. - interrupt controller with 6 hardware interrupt signals. - - 3 HW-level nested interruptions. - - User and super-user mode support. - - Memory-mapped I/O. - - Address space up to 4GB. - -Memory Management Unit - - TLB - - 4/8-entry fully associative iTLB/dTLB. - - 32/64/128-entry 4-way set-associati.ve main TLB. - - TLB locking support - - Optional hardware page table walker. - - Two groups of page size support. - - 4KB & 1MB. - - 8KB & 1MB. - -Memory Subsystem - - I & D cache. - - Virtually indexed and physically tagged. - - Cache size: 8KB/16KB/32KB/64KB. - - Cache line size: 16B/32B. - - Set associativity: 2-way, 4-way or direct-mapped. - - Cache locking support. - - I & D local memory (LM). - - Size: 4KB to 1MB. - - Bank numbers: 1 or 2. - - Optional 1D/2D DMA engine. - - Internal or external to CPU core. - -Bus Interface - - Synchronous/Asynchronous AHB bus: 0, 1 or 2 ports. - - Synchronous High speed memory port. - (HSMP): 0, 1 or 2 ports. - -Debug - - JTAG debug interface. - - Embedded debug module (EDM). - - Optional embedded program tracer interface. - -Miscellaneous - - Programmable data endian control. - - Performance monitoring mechanism. diff --git a/doc/README.NDS32 b/doc/README.NDS32 deleted file mode 100644 index b2b58fc..0000000 --- a/doc/README.NDS32 +++ /dev/null @@ -1,41 +0,0 @@ -NDS32 is a new high-performance 32-bit RISC microprocessor core. - -http://www.andestech.com/ - -AndeStar ISA -============ -AndeStar is a patent-pending 16-bit/32-bit mixed-length instruction set to -achieve optimal system performance, code density, and power efficiency. - -It contains the following features: - - Intermixable 32-bit and 16-bit instruction sets without the need for - mode switch. - - 16-bit instructions as a frequently used subset of 32-bit instructions. - - RISC-style register-based instruction set. - - 32 32-bit General Purpose Registers (GPR). - - Upto 1024 User Special Registers (USR) for existing and extension - instructions. - - Rich load/store instructions for... - - Single memory access with base address update. - - Multiple aligned and unaligned memory accesses for memory copy and stack - operations. - - Data prefetch to improve data cache performance. - - Non-bus locking synchronization instructions. - - PC relative jump and PC read instructions for efficient position independent - code. - - Multiply-add and multiple-sub with 64-bit accumulator. - - Instruction for efficient power management. - - Bi-endian support. - - Three instruction extension space for application acceleration: - - Performance extension. - - Andes future extensions (for floating-point, multimedia, etc.) - - Customer extensions. - -AndesCore CPU -============= -Andes Technology has 4 families of CPU cores: N12, N10, N9, N8. - -For details about N12 CPU family, please check doc/README.N1213. - -The NDS32 ports of u-boot, the Linux kernel, the GNU toolchain and -other associated software are actively supported by Andes Technology Corporation. diff --git a/doc/arch/index.rst b/doc/arch/index.rst index 360b5d9..7f10df0 100644 --- a/doc/arch/index.rst +++ b/doc/arch/index.rst @@ -8,4 +8,5 @@ Architecture-specific doc arm64 mips + nds32 x86 diff --git a/doc/arch/nds32.rst b/doc/arch/nds32.rst new file mode 100644 index 0000000..502397c --- /dev/null +++ b/doc/arch/nds32.rst @@ -0,0 +1,101 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +NDS32 +===== + +NDS32 is a new high-performance 32-bit RISC microprocessor core. + +http://www.andestech.com/ + +AndeStar ISA +------------ +AndeStar is a patent-pending 16-bit/32-bit mixed-length instruction set to +achieve optimal system performance, code density, and power efficiency. + +It contains the following features: + - Intermixable 32-bit and 16-bit instruction sets without the need for + mode switch. + - 16-bit instructions as a frequently used subset of 32-bit instructions. + - RISC-style register-based instruction set. + - 32 32-bit General Purpose Registers (GPR). + - Upto 1024 User Special Registers (USR) for existing and extension + instructions. + - Rich load/store instructions for... + - Single memory access with base address update. + - Multiple aligned and unaligned memory accesses for memory copy and stack + operations. + - Data prefetch to improve data cache performance. + - Non-bus locking synchronization instructions. + - PC relative jump and PC read instructions for efficient position independent + code. + - Multiply-add and multiple-sub with 64-bit accumulator. + - Instruction for efficient power management. + - Bi-endian support. + - Three instruction extension space for application acceleration: + - Performance extension. + - Andes future extensions (for floating-point, multimedia, etc.) + - Customer extensions. + +AndesCore CPU +------------- +Andes Technology has 4 families of CPU cores: N12, N10, N9, N8. + +For details about N12 CPU family, please check below N1213 features. +N1213 is a configurable hard/soft core of NDS32's N12 CPU family. + +N1213 Features +^^^^^^^^^^^^^^ + +CPU Core + - 16-/32-bit mixable instruction format. + - 32 general-purpose 32-bit registers. + - 8-stage pipeline. + - Dynamic branch prediction. + - 32/64/128/256 BTB. + - Return address stack (RAS). + - Vector interrupts for internal/external. + interrupt controller with 6 hardware interrupt signals. + - 3 HW-level nested interruptions. + - User and super-user mode support. + - Memory-mapped I/O. + - Address space up to 4GB. + +Memory Management Unit + - TLB + - 4/8-entry fully associative iTLB/dTLB. + - 32/64/128-entry 4-way set-associati.ve main TLB. + - TLB locking support + - Optional hardware page table walker. + - Two groups of page size support. + - 4KB & 1MB. + - 8KB & 1MB. + +Memory Subsystem + - I & D cache. + - Virtually indexed and physically tagged. + - Cache size: 8KB/16KB/32KB/64KB. + - Cache line size: 16B/32B. + - Set associativity: 2-way, 4-way or direct-mapped. + - Cache locking support. + - I & D local memory (LM). + - Size: 4KB to 1MB. + - Bank numbers: 1 or 2. + - Optional 1D/2D DMA engine. + - Internal or external to CPU core. + +Bus Interface + - Synchronous/Asynchronous AHB bus: 0, 1 or 2 ports. + - Synchronous High speed memory port. + (HSMP): 0, 1 or 2 ports. + +Debug + - JTAG debug interface. + - Embedded debug module (EDM). + - Optional embedded program tracer interface. + +Miscellaneous + - Programmable data endian control. + - Performance monitoring mechanism. + +The NDS32 ports of u-boot, the Linux kernel, the GNU toolchain and other +associated software are actively supported by Andes Technology Corporation.