From patchwork Thu Jul 18 07:34:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1133586 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Cv5miF/u"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 45q5mP6TWJz9s00 for ; Thu, 18 Jul 2019 17:46:13 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 9F2D2C2205D; Thu, 18 Jul 2019 07:40:48 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 52D26C21F48; Thu, 18 Jul 2019 07:35:37 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 52ED0C21F8F; Thu, 18 Jul 2019 07:35:17 +0000 (UTC) Received: from mail-pg1-f194.google.com (mail-pg1-f194.google.com [209.85.215.194]) by lists.denx.de (Postfix) with ESMTPS id CBCFAC21F48 for ; Thu, 18 Jul 2019 07:35:11 +0000 (UTC) Received: by mail-pg1-f194.google.com with SMTP id l21so12475782pgm.3 for ; Thu, 18 Jul 2019 00:35:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=rfKdB4GdAnr+PBUh3ksdwWVeqAi5d7TTQWlCczwJcyU=; b=Cv5miF/uqCAJVAC/64m3r7j3NWFzY8S78R9TDjMTD76JWI0FYXMZ6RhysPJCl9C7wn BsPfIoGapwye5H4Fue17UWXApbdlWJiDn6G9gSmCojsYosfEseX8Lwo8gM8nMHK25SpJ v3vKXzwwqlptaOLi2eYXrV5NpiYTCxEtIt0REvcPbepZ1ysJfsupwJhmL2AzTjbeNUXA cUBHMzBEHnhjVJjVQ+aE7+RkFswpRWYQq7YuttC+svySwoh9wJneP5Y5+Tkb7mJNWJZ1 zU/VQU8pJ+WwBlSTB4Bhz6s2JcsbGskozIwoaeLkHAeREg1mUzBHBkm291G39EgGY2MT jZVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=rfKdB4GdAnr+PBUh3ksdwWVeqAi5d7TTQWlCczwJcyU=; b=H9KYcWuvBIXOPbVhcw/Xq1oWEtte+yXPFt4Zfj25137ESZtN3GPgl3K1d6BqYx5VzO trl6lBeNlAfa+DcHUyZOaW0pYs/dmIEAbMQ7rg5jimopbjCq3pPgDTe+3QHw95oTPFz0 NN8jUVilFuF9DXNRjrB5YtJUNREOCkKzqDfF5BoEgWzfynZcIGqLZWhkIG5cvbxHwC16 HdMumvzh7tw+ARSVSvny4NB8qabewh5YmPIcSu0BnuJKEXAoLxGTZfigORmkVMAvbbNA wLtgFh/C7orDVo2aN7zuYs+oVJHAQb3k3TqLoQUJsmCGDEysq36BIWDUk91+64dfRGHI XkVA== X-Gm-Message-State: APjAAAUhH1cIq1Glme/aoZcUNAy91uVnuEoSm25GgrriJ5FVo1WKp7qp lrMvWeTFRWnnlZZJUOlmyPU= X-Google-Smtp-Source: APXvYqyDRVSTE6IKSZib53A45U8GglOMdwhZXSFP9QXSdogdFWp7G6KkgmI3xqqqBq57EmnQzsQekQ== X-Received: by 2002:a17:90a:a116:: with SMTP id s22mr49043111pjp.47.1563435305939; Thu, 18 Jul 2019 00:35:05 -0700 (PDT) Received: from localhost.localdomain (unknown-224-80.windriver.com. [147.11.224.80]) by smtp.gmail.com with ESMTPSA id q1sm39859821pfn.178.2019.07.18.00.35.04 (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 18 Jul 2019 00:35:05 -0700 (PDT) From: Bin Meng To: Tom Rini , Simon Glass , Wolfgang Denk , Heinrich Schuchardt , Mario Six , U-Boot Mailing List Date: Thu, 18 Jul 2019 00:34:07 -0700 Message-Id: <1563435275-22326-23-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1563435275-22326-1-git-send-email-bmeng.cn@gmail.com> References: <1563435275-22326-1-git-send-email-bmeng.cn@gmail.com> Subject: [U-Boot] [PATCH 22/50] doc: board: Add Intel Cherry Hill board doc X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This extracts Intel Cherry Hill board specific information from README.x86, converts plain text documentation to reST format and adds it to Sphinx TOC tree. No essential content change. Signed-off-by: Bin Meng --- doc/README.x86 | 29 ----------------------------- doc/board/intel/cherryhill.rst | 30 ++++++++++++++++++++++++++++++ doc/board/intel/index.rst | 1 + 3 files changed, 31 insertions(+), 29 deletions(-) create mode 100644 doc/board/intel/cherryhill.rst diff --git a/doc/README.x86 b/doc/README.x86 index b4f0f7c..8e549c3 100644 --- a/doc/README.x86 +++ b/doc/README.x86 @@ -226,35 +226,6 @@ to the last 2MB of the 8MB chip, address range [600000, 7FFFFF]. --- -Intel Cherry Hill specific instructions for bare mode: - -This uses Intel FSP for Braswell platform. Download it from Intel FSP website, -put the .fd file to the board directory and rename it to fsp.bin. - -Extract descriptor.bin and me.bin from the original BIOS on the board using -ifdtool and put them to the board directory as well. - -Note the FSP package for Braswell does not ship a traditional legacy VGA BIOS -image for the integrated graphics device. Instead a new binary called Video -BIOS Table (VBT) is shipped. Put it to the board directory and rename it to -vbt.bin if you want graphics support in U-Boot. - -Now you can build U-Boot and obtain u-boot.rom - -$ make cherryhill_defconfig -$ make all - -An important note for programming u-boot.rom to the on-board SPI flash is that -you need make sure the SPI flash's 'quad enable' bit in its status register -matches the settings in the descriptor.bin, otherwise the board won't boot. - -For the on-board SPI flash MX25U6435F, this can be done by writing 0x40 to the -status register by DediProg in: Config > Modify Status Register > Write Status -Register(s) > Register1 Value(Hex). This is is a one-time change. Once set, it -persists in SPI flash part regardless of the u-boot.rom image burned. - ---- - Intel Galileo instructions for bare mode: Only one binary blob is needed for Remote Management Unit (RMU) within Intel diff --git a/doc/board/intel/cherryhill.rst b/doc/board/intel/cherryhill.rst new file mode 100644 index 0000000..151f061 --- /dev/null +++ b/doc/board/intel/cherryhill.rst @@ -0,0 +1,30 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. sectionauthor:: Bin Meng + +Cherry Hill CRB +=============== + +This uses Intel FSP for Braswell platform. Download it from Intel FSP website, +put the .fd file to the board directory and rename it to fsp.bin. + +Extract descriptor.bin and me.bin from the original BIOS on the board using +ifdtool and put them to the board directory as well. + +Note the FSP package for Braswell does not ship a traditional legacy VGA BIOS +image for the integrated graphics device. Instead a new binary called Video +BIOS Table (VBT) is shipped. Put it to the board directory and rename it to +vbt.bin if you want graphics support in U-Boot. + +Now you can build U-Boot and obtain u-boot.rom:: + + $ make cherryhill_defconfig + $ make all + +An important note for programming u-boot.rom to the on-board SPI flash is that +you need make sure the SPI flash's 'quad enable' bit in its status register +matches the settings in the descriptor.bin, otherwise the board won't boot. + +For the on-board SPI flash MX25U6435F, this can be done by writing 0x40 to the +status register by DediProg in: Config > Modify Status Register > Write Status +Register(s) > Register1 Value(Hex). This is is a one-time change. Once set, it +persists in SPI flash part regardless of the u-boot.rom image burned. diff --git a/doc/board/intel/index.rst b/doc/board/intel/index.rst index af24760..d30debb 100644 --- a/doc/board/intel/index.rst +++ b/doc/board/intel/index.rst @@ -7,5 +7,6 @@ Intel :maxdepth: 2 bayleybay + cherryhill crownbay minnowmax