[U-Boot,23/50] doc: board: Add Intel Cougar Canyon 2 board doc
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Message ID 1563435275-22326-24-git-send-email-bmeng.cn@gmail.com
State Accepted
Commit 87fdda62cd15c9231b3b7c1da7f9c333497ae17e
Delegated to: Tom Rini
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Series
  • doc: Shape into useful HTML docs
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Commit Message

Bin Meng July 18, 2019, 7:34 a.m. UTC
This extracts Intel Cougar Canyon 2 board specific information from
README.x86, converts plain text documentation to reST format and
adds it to Sphinx TOC tree. No essential content change.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

 doc/README.x86                    | 23 -----------------------
 doc/board/intel/cougarcanyon2.rst | 24 ++++++++++++++++++++++++
 doc/board/intel/index.rst         |  1 +
 3 files changed, 25 insertions(+), 23 deletions(-)
 create mode 100644 doc/board/intel/cougarcanyon2.rst

Patch
diff mbox series

diff --git a/doc/README.x86 b/doc/README.x86
index 8e549c3..5e85b57 100644
--- a/doc/README.x86
+++ b/doc/README.x86
@@ -203,29 +203,6 @@  Flash map for samus / broadwell:
 
 ---
 
-Intel Cougar Canyon 2 specific instructions for bare mode:
-
-This uses Intel FSP for 3rd generation Intel Core and Intel Celeron processors
-with mobile Intel HM76 and QM77 chipsets platform. Download it from Intel FSP
-website and put the .fd file (CHIEFRIVER_FSP_GOLD_001_09-OCTOBER-2013.fd at the
-time of writing) in the board directory and rename it to fsp.bin.
-
-Now build U-Boot and obtain u-boot.rom
-
-$ make cougarcanyon2_defconfig
-$ make all
-
-The board has two 8MB SPI flashes mounted, which are called SPI-0 and SPI-1 in
-the board manual. The SPI-0 flash should have flash descriptor plus ME firmware
-and SPI-1 flash is used to store U-Boot. For convenience, the complete 8MB SPI-0
-flash image is included in the FSP package (named Rom00_8M_MB_PPT.bin). Program
-this image to the SPI-0 flash according to the board manual just once and we are
-all set. For programming U-Boot we just need to program SPI-1 flash. Since the
-default u-boot.rom image for this board is set to 2MB, it should be programmed
-to the last 2MB of the 8MB chip, address range [600000, 7FFFFF].
-
----
-
 Intel Galileo instructions for bare mode:
 
 Only one binary blob is needed for Remote Management Unit (RMU) within Intel
diff --git a/doc/board/intel/cougarcanyon2.rst b/doc/board/intel/cougarcanyon2.rst
new file mode 100644
index 0000000..5e3e7a1
--- /dev/null
+++ b/doc/board/intel/cougarcanyon2.rst
@@ -0,0 +1,24 @@ 
+.. SPDX-License-Identifier: GPL-2.0+
+.. sectionauthor:: Bin Meng <bmeng.cn@gmail.com>
+
+Cougar Canyon 2 CRB
+===================
+
+This uses Intel FSP for 3rd generation Intel Core and Intel Celeron processors
+with mobile Intel HM76 and QM77 chipsets platform. Download it from Intel FSP
+website and put the .fd file (CHIEFRIVER_FSP_GOLD_001_09-OCTOBER-2013.fd at the
+time of writing) in the board directory and rename it to fsp.bin.
+
+Now build U-Boot and obtain u-boot.rom::
+
+   $ make cougarcanyon2_defconfig
+   $ make all
+
+The board has two 8MB SPI flashes mounted, which are called SPI-0 and SPI-1 in
+the board manual. The SPI-0 flash should have flash descriptor plus ME firmware
+and SPI-1 flash is used to store U-Boot. For convenience, the complete 8MB SPI-0
+flash image is included in the FSP package (named Rom00_8M_MB_PPT.bin). Program
+this image to the SPI-0 flash according to the board manual just once and we are
+all set. For programming U-Boot we just need to program SPI-1 flash. Since the
+default u-boot.rom image for this board is set to 2MB, it should be programmed
+to the last 2MB of the 8MB chip, address range [600000, 7FFFFF].
diff --git a/doc/board/intel/index.rst b/doc/board/intel/index.rst
index d30debb..521e6e6 100644
--- a/doc/board/intel/index.rst
+++ b/doc/board/intel/index.rst
@@ -8,5 +8,6 @@  Intel
 
    bayleybay
    cherryhill
+   cougarcanyon2
    crownbay
    minnowmax