From patchwork Mon Sep 5 11:47:06 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Helmut Raiger X-Patchwork-Id: 113340 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 74034B6F85 for ; Mon, 5 Sep 2011 21:48:00 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 8AF7E2809F; Mon, 5 Sep 2011 13:47:48 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 0hsoDFPrHiJc; Mon, 5 Sep 2011 13:47:48 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 454F828088; Mon, 5 Sep 2011 13:47:39 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 591AB2807F for ; Mon, 5 Sep 2011 13:47:37 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id EADTEXgm8ALp for ; Mon, 5 Sep 2011 13:47:36 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mx.inode.at (mx03.lb01.inode.at [62.99.145.3]) by theia.denx.de (Postfix) with ESMTPS id 033C528080 for ; Mon, 5 Sep 2011 13:47:34 +0200 (CEST) Received: from [83.64.51.210] (port=15639 helo=gateway1.hale) by smartmx-03.inode.at with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.69) (envelope-from ) id 1R0XeI-00066P-8l; Mon, 05 Sep 2011 13:47:34 +0200 Received: from mail1.hale.at (mail2.hale [192.168.100.12]) by gateway1.hale (8.13.8/8.13.7) with ESMTP id p85BlTaU016170; Mon, 5 Sep 2011 13:47:29 +0200 Received: from uni24.HALE ([192.168.100.40]) by hale.at with MailEnable ESMTP; Mon, 5 Sep 2011 13:47:24 +0200 From: Helmut Raiger To: u-boot@lists.denx.de Date: Mon, 5 Sep 2011 13:47:06 +0200 Message-Id: <1315223227-29535-2-git-send-email-helmut.raiger@hale.at> X-Mailer: git-send-email 1.7.4.4 In-Reply-To: <1315223227-29535-1-git-send-email-helmut.raiger@hale.at> References: <1314020497-30897-1-git-send-email-helmut.raiger@hale.at> <1315223227-29535-1-git-send-email-helmut.raiger@hale.at> MIME-Version: 1.0 X-HALE-MailScanner-Information: Please contact the ISP for more information X-MailScanner-ID: p85BlTaU016170 X-HALE-MailScanner: Found to be clean X-HALE-MailScanner-From: helmut.raiger@hale.at MailScanner-NULL-Check: 1315828052.77772@vjrM/r4eAojrw/uxWZyQGw Subject: [U-Boot] [PATCH 1/2] mx31: make HSP clock for mx3fb driver available X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de This additionally updates mx31/generic.c by - replacing __REG() macro accesses with readl() and writel() - providing macros for PDR0 and PLL bit accesses It also fixes a warning about the prototype of imx_get_uartclk(void) Signed-off-by: Helmut Raiger Acked-by: Marek Vasut --- V2: uses macros and readl(), writel(), see commit message arch/arm/cpu/arm1136/mx31/generic.c | 40 +++++++++++++++++++--------- arch/arm/include/asm/arch-mx31/clock.h | 3 +- arch/arm/include/asm/arch-mx31/imx-regs.h | 14 ++++++++++ 3 files changed, 43 insertions(+), 14 deletions(-) diff --git a/arch/arm/cpu/arm1136/mx31/generic.c b/arch/arm/cpu/arm1136/mx31/generic.c index 248431b..9a7612b 100644 --- a/arch/arm/cpu/arm1136/mx31/generic.c +++ b/arch/arm/cpu/arm1136/mx31/generic.c @@ -28,10 +28,10 @@ static u32 mx31_decode_pll(u32 reg, u32 infreq) { - u32 mfi = (reg >> 10) & 0xf; - u32 mfn = reg & 0x3ff; - u32 mfd = (reg >> 16) & 0x3ff; - u32 pd = (reg >> 26) & 0xf; + u32 mfi = GET_PLL_MFI(reg); + u32 mfn = GET_PLL_MFN(reg); + u32 mfd = GET_PLL_MFD(reg); + u32 pd = GET_PLL_PD(reg); mfi = mfi <= 5 ? 5 : mfi; mfd += 1; @@ -45,12 +45,12 @@ static u32 mx31_get_mpl_dpdgck_clk(void) { u32 infreq; - if ((__REG(CCM_CCMR) & CCMR_PRCS_MASK) == CCMR_FPM) + if ((readl(CCM_CCMR) & CCMR_PRCS_MASK) == CCMR_FPM) infreq = CONFIG_MX31_CLK32 * 1024; else infreq = CONFIG_MX31_HCLK_FREQ; - return mx31_decode_pll(__REG(CCM_MPCTL), infreq); + return mx31_decode_pll(readl(CCM_MPCTL), infreq); } static u32 mx31_get_mcu_main_clk(void) @@ -64,10 +64,21 @@ static u32 mx31_get_mcu_main_clk(void) static u32 mx31_get_ipg_clk(void) { u32 freq = mx31_get_mcu_main_clk(); - u32 pdr0 = __REG(CCM_PDR0); + u32 pdr0 = readl(CCM_PDR0); - freq /= ((pdr0 >> 3) & 0x7) + 1; - freq /= ((pdr0 >> 6) & 0x3) + 1; + freq /= GET_PDR0_MAX_PODF(pdr0) + 1; + freq /= GET_PDR0_IPG_PODF(pdr0) + 1; + + return freq; +} + +/* hsp is the clock for the ipu */ +static u32 mx31_get_hsp_clk(void) +{ + u32 freq = mx31_get_mcu_main_clk(); + u32 pdr0 = readl(CCM_PDR0); + + freq /= GET_PDR0_HSP_PODF(pdr0) + 1; return freq; } @@ -77,6 +88,7 @@ void mx31_dump_clocks(void) u32 cpufreq = mx31_get_mcu_main_clk(); printf("mx31 cpu clock: %dMHz\n",cpufreq / 1000000); printf("ipg clock : %dHz\n", mx31_get_ipg_clk()); + printf("hsp clock : %dHz\n", mx31_get_hsp_clk()); } unsigned int mxc_get_clock(enum mxc_clock clk) @@ -88,6 +100,8 @@ unsigned int mxc_get_clock(enum mxc_clock clk) case MXC_CSPI_CLK: case MXC_UART_CLK: return mx31_get_ipg_clk(); + case MXC_IPU_CLK: + return mx31_get_hsp_clk(); } return -1; } @@ -104,10 +118,10 @@ void mx31_gpio_mux(unsigned long mode) reg = IOMUXC_BASE + (mode & 0x1fc); shift = (~mode & 0x3) * 8; - tmp = __REG(reg); + tmp = readl(reg); tmp &= ~(0xff << shift); tmp |= ((mode >> IOMUX_MODE_POS) & 0xff) << shift; - __REG(reg) = tmp; + writel(tmp, reg); } void mx31_set_pad(enum iomux_pins pin, u32 config) @@ -118,10 +132,10 @@ void mx31_set_pad(enum iomux_pins pin, u32 config) reg = (IOMUXC_BASE + 0x154) + (pin + 2) / 3 * 4; field = (pin + 2) % 3; - l = __REG(reg); + l = readl(reg); l &= ~(0x1ff << (field * 10)); l |= config << (field * 10); - __REG(reg) = l; + writel(l, reg); } diff --git a/arch/arm/include/asm/arch-mx31/clock.h b/arch/arm/include/asm/arch-mx31/clock.h index fb035c4..1ea5a47 100644 --- a/arch/arm/include/asm/arch-mx31/clock.h +++ b/arch/arm/include/asm/arch-mx31/clock.h @@ -29,10 +29,11 @@ enum mxc_clock { MXC_IPG_CLK, MXC_CSPI_CLK, MXC_UART_CLK, + MXC_IPU_CLK }; unsigned int mxc_get_clock(enum mxc_clock clk); -extern u32 imx_get_uartclk(); +extern u32 imx_get_uartclk(void); extern void mx31_gpio_mux(unsigned long mode); extern void mx31_set_pad(enum iomux_pins pin, u32 config); diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h index 3c8d607..c24dae2 100644 --- a/arch/arm/include/asm/arch-mx31/imx-regs.h +++ b/arch/arm/include/asm/arch-mx31/imx-regs.h @@ -518,6 +518,20 @@ enum iomux_pins { #define PLL_MFI(x) (((x) & 0xf) << 10) #define PLL_MFN(x) (((x) & 0x3ff) << 0) +#define GET_PDR0_CSI_PODF(x) (((x) >> 23) & 0x1ff) +#define GET_PDR0_PER_PODF(x) (((x) >> 16) & 0x1f) +#define GET_PDR0_HSP_PODF(x) (((x) >> 11) & 0x7) +#define GET_PDR0_NFC_PODF(x) (((x) >> 8) & 0x7) +#define GET_PDR0_IPG_PODF(x) (((x) >> 6) & 0x3) +#define GET_PDR0_MAX_PODF(x) (((x) >> 3) & 0x7) +#define GET_PDR0_MCU_PODF(x) ((x) & 0x7) + +#define GET_PLL_PD(x) (((x) >> 26) & 0xf) +#define GET_PLL_MFD(x) (((x) >> 16) & 0x3ff) +#define GET_PLL_MFI(x) (((x) >> 10) & 0xf) +#define GET_PLL_MFN(x) (((x) >> 0) & 0x3ff) + + #define WEIM_ESDCTL0 0xB8001000 #define WEIM_ESDCFG0 0xB8001004 #define WEIM_ESDCTL1 0xB8001008