Message ID | 20190716115745.12585-49-jagan@amarulasolutions.com |
---|---|
State | Accepted |
Commit | f556d75aeda352d10d8b502056d5e22c79b063f0 |
Delegated to: | Kever Yang |
Headers | show |
Series | ram: rk3399: Add LPDDR4 support | expand |
On 2019/7/16 下午7:57, Jagan Teki wrote: > Add support for setting 400MHz ddr clock. > > Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> > Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com> Thanks, - Kever > --- > drivers/clk/rockchip/clk_rk3399.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c > index 1de21c9f3e..79007b8682 100644 > --- a/drivers/clk/rockchip/clk_rk3399.c > +++ b/drivers/clk/rockchip/clk_rk3399.c > @@ -839,6 +839,10 @@ static ulong rk3399_ddr_set_clk(struct rk3399_cru *cru, > dpll_cfg = (struct pll_div) > {.refdiv = 2, .fbdiv = 100, .postdiv1 = 4, .postdiv2 = 1}; > break; > + case 400 * MHz: > + dpll_cfg = (struct pll_div) > + {.refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 1}; > + break; > case 666 * MHz: > dpll_cfg = (struct pll_div) > {.refdiv = 2, .fbdiv = 111, .postdiv1 = 2, .postdiv2 = 1};
diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 1de21c9f3e..79007b8682 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -839,6 +839,10 @@ static ulong rk3399_ddr_set_clk(struct rk3399_cru *cru, dpll_cfg = (struct pll_div) {.refdiv = 2, .fbdiv = 100, .postdiv1 = 4, .postdiv2 = 1}; break; + case 400 * MHz: + dpll_cfg = (struct pll_div) + {.refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 1}; + break; case 666 * MHz: dpll_cfg = (struct pll_div) {.refdiv = 2, .fbdiv = 111, .postdiv1 = 2, .postdiv2 = 1};