diff mbox series

TCG - Allow bit 15 to 1 for slbmfee and slbmfev

Message ID 4791ac27-8a85-7d08-85a6-193a988f60be@vmfacility.fr
State New
Headers show
Series TCG - Allow bit 15 to 1 for slbmfee and slbmfev | expand

Commit Message

Cameron Esfahani via July 16, 2019, 7:12 a.m. UTC 
All,

Submitting proposal :

Per Power ISA 3.02B Book III at pages 1029 and 1030, bit 15 of the 
slbmfee and slbmfev instructions is now assigned to an implementation 
specific bit and is no longer reserved - meaning it can be set to 1 but 
can probably be safely ignored.

2.07B still indicates bit 15 is reserved but some non Linux Operating 
system's debugger DO set this bit to 1 (so it was probably valid yet not 
documented for Power 7/8).

Therefore I propose :

PPC_SEGMENT_64B),
+GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001E0001, 
PPC_SEGMENT_64B),
  GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, 
PPC_SEGMENT_64B),
  #endif
  GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),

PS : This patch is not mine, but gleaned from "Zhuowei Zhang" (no known 
e-mail address). I am just attempting to have it validated.
diff mbox series

Patch

diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 4a5de28036..85f8b147ba 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -7064,8 +7064,8 @@  GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 
0x0010F801, PPC_SEGMENT_64B),
  GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
               PPC_SEGMENT_64B),
  GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, 
PPC_SEGMENT_64B),
-GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, 
PPC_SEGMENT_64B),
-GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, 
PPC_SEGMENT_64B),
+GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001E0001,