[v2] clocksource/drivers/npcm: fix GENMASK and timer operation
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Message ID CAKKbWA5nwsa5kcZ8GCuC3WKJptb6RtZ65izFphd=KaALqeg+BA@mail.gmail.com
State New
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  • [v2] clocksource/drivers/npcm: fix GENMASK and timer operation
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Commit Message

Avi Fishman July 15, 2019, 3:19 p.m. UTC
clocksource/drivers/npcm: fix GENMASK and timer operation

NPCM7XX_Tx_OPER GENMASK() changed from (27, 3) to (28, 27)

in npcm7xx_timer_oneshot() the original NPCM7XX_REG_TCSR0 register was
read again after masking it with ~NPCM7XX_Tx_OPER so the masking didn't
take effect.

npcm7xx_timer_periodic() was not wrong but it wrote to NPCM7XX_REG_TICR0
in a middle of read modify write to NPCM7XX_REG_TCSR0 which is
confusing.

Signed-off-by: Avi Fishman <avifishman70@gmail.com>
---
 drivers/clocksource/timer-npcm7xx.c | 9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)


@@ -97,12 +95,11 @@ static int npcm7xx_timer_periodic(struct
clock_event_device *evt)
        struct timer_of *to = to_timer_of(evt);
        u32 val;

+       writel(timer_of_period(to), timer_of_base(to) + NPCM7XX_REG_TICR0);
+
        val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);
        val &= ~NPCM7XX_Tx_OPER;
-
-       writel(timer_of_period(to), timer_of_base(to) + NPCM7XX_REG_TICR0);
        val |= NPCM7XX_START_PERIODIC_Tx;
-
        writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0);

        return 0;

Comments

Joe Perches July 15, 2019, 3:25 p.m. UTC | #1
On Mon, 2019-07-15 at 18:19 +0300, Avi Fishman wrote:
> clocksource/drivers/npcm: fix GENMASK and timer operation
> 
> NPCM7XX_Tx_OPER GENMASK() changed from (27, 3) to (28, 27)
> 
> in npcm7xx_timer_oneshot() the original NPCM7XX_REG_TCSR0 register was
> read again after masking it with ~NPCM7XX_Tx_OPER so the masking didn't
> take effect.
> 
> npcm7xx_timer_periodic() was not wrong but it wrote to NPCM7XX_REG_TICR0
> in a middle of read modify write to NPCM7XX_REG_TCSR0 which is
> confusing.

You might mention how the original use of GENMASK(3, 27)
was defective or correct without effect.

> Signed-off-by: Avi Fishman <avifishman70@gmail.com>
> ---
>  drivers/clocksource/timer-npcm7xx.c | 9 +++------
>  1 file changed, 3 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/clocksource/timer-npcm7xx.c
> b/drivers/clocksource/timer-npcm7xx.c
> index 8a30da7f083b..9780ffd8010e 100644
> --- a/drivers/clocksource/timer-npcm7xx.c
> +++ b/drivers/clocksource/timer-npcm7xx.c
> @@ -32,7 +32,7 @@
>  #define NPCM7XX_Tx_INTEN               BIT(29)
>  #define NPCM7XX_Tx_COUNTEN             BIT(30)
>  #define NPCM7XX_Tx_ONESHOT             0x0
> -#define NPCM7XX_Tx_OPER                        GENMASK(27, 3)
> +#define NPCM7XX_Tx_OPER                        GENMASK(28, 27)
>  #define NPCM7XX_Tx_MIN_PRESCALE                0x1
>  #define NPCM7XX_Tx_TDR_MASK_BITS       24
>  #define NPCM7XX_Tx_MAX_CNT             0xFFFFFF
> @@ -84,8 +84,6 @@ static int npcm7xx_timer_oneshot(struct
> clock_event_device *evt)
> 
>         val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);
>         val &= ~NPCM7XX_Tx_OPER;
> -
> -       val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);
>         val |= NPCM7XX_START_ONESHOT_Tx;
>         writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0);
> 
> @@ -97,12 +95,11 @@ static int npcm7xx_timer_periodic(struct
> clock_event_device *evt)
>         struct timer_of *to = to_timer_of(evt);
>         u32 val;
> 
> +       writel(timer_of_period(to), timer_of_base(to) + NPCM7XX_REG_TICR0);
> +
>         val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);
>         val &= ~NPCM7XX_Tx_OPER;
> -
> -       writel(timer_of_period(to), timer_of_base(to) + NPCM7XX_REG_TICR0);
>         val |= NPCM7XX_START_PERIODIC_Tx;
> -
>         writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0);
> 
>         return 0;
>
Avi Fishman July 15, 2019, 3:48 p.m. UTC | #2
On Mon, Jul 15, 2019 at 6:25 PM Joe Perches <joe@perches.com> wrote:
>
> On Mon, 2019-07-15 at 18:19 +0300, Avi Fishman wrote:
> > clocksource/drivers/npcm: fix GENMASK and timer operation
> >
> > NPCM7XX_Tx_OPER GENMASK() changed from (27, 3) to (28, 27)
> >
> > in npcm7xx_timer_oneshot() the original NPCM7XX_REG_TCSR0 register was
> > read again after masking it with ~NPCM7XX_Tx_OPER so the masking didn't
> > take effect.
> >
> > npcm7xx_timer_periodic() was not wrong but it wrote to NPCM7XX_REG_TICR0
> > in a middle of read modify write to NPCM7XX_REG_TCSR0 which is
> > confusing.
>
> You might mention how the original use of GENMASK(3, 27)
> was defective or correct without effect.

Done, see v3 of this patch.

>
> > Signed-off-by: Avi Fishman <avifishman70@gmail.com>
> > ---
> >  drivers/clocksource/timer-npcm7xx.c | 9 +++------
> >  1 file changed, 3 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/clocksource/timer-npcm7xx.c
> > b/drivers/clocksource/timer-npcm7xx.c
> > index 8a30da7f083b..9780ffd8010e 100644
> > --- a/drivers/clocksource/timer-npcm7xx.c
> > +++ b/drivers/clocksource/timer-npcm7xx.c
> > @@ -32,7 +32,7 @@
> >  #define NPCM7XX_Tx_INTEN               BIT(29)
> >  #define NPCM7XX_Tx_COUNTEN             BIT(30)
> >  #define NPCM7XX_Tx_ONESHOT             0x0
> > -#define NPCM7XX_Tx_OPER                        GENMASK(27, 3)
> > +#define NPCM7XX_Tx_OPER                        GENMASK(28, 27)
> >  #define NPCM7XX_Tx_MIN_PRESCALE                0x1
> >  #define NPCM7XX_Tx_TDR_MASK_BITS       24
> >  #define NPCM7XX_Tx_MAX_CNT             0xFFFFFF
> > @@ -84,8 +84,6 @@ static int npcm7xx_timer_oneshot(struct
> > clock_event_device *evt)
> >
> >         val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);
> >         val &= ~NPCM7XX_Tx_OPER;
> > -
> > -       val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);
> >         val |= NPCM7XX_START_ONESHOT_Tx;
> >         writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0);
> >
> > @@ -97,12 +95,11 @@ static int npcm7xx_timer_periodic(struct
> > clock_event_device *evt)
> >         struct timer_of *to = to_timer_of(evt);
> >         u32 val;
> >
> > +       writel(timer_of_period(to), timer_of_base(to) + NPCM7XX_REG_TICR0);
> > +
> >         val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);
> >         val &= ~NPCM7XX_Tx_OPER;
> > -
> > -       writel(timer_of_period(to), timer_of_base(to) + NPCM7XX_REG_TICR0);
> >         val |= NPCM7XX_START_PERIODIC_Tx;
> > -
> >         writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0);
> >
> >         return 0;
> >
>

Patch
diff mbox series

diff --git a/drivers/clocksource/timer-npcm7xx.c
b/drivers/clocksource/timer-npcm7xx.c
index 8a30da7f083b..9780ffd8010e 100644
--- a/drivers/clocksource/timer-npcm7xx.c
+++ b/drivers/clocksource/timer-npcm7xx.c
@@ -32,7 +32,7 @@ 
 #define NPCM7XX_Tx_INTEN               BIT(29)
 #define NPCM7XX_Tx_COUNTEN             BIT(30)
 #define NPCM7XX_Tx_ONESHOT             0x0
-#define NPCM7XX_Tx_OPER                        GENMASK(27, 3)
+#define NPCM7XX_Tx_OPER                        GENMASK(28, 27)
 #define NPCM7XX_Tx_MIN_PRESCALE                0x1
 #define NPCM7XX_Tx_TDR_MASK_BITS       24
 #define NPCM7XX_Tx_MAX_CNT             0xFFFFFF
@@ -84,8 +84,6 @@  static int npcm7xx_timer_oneshot(struct
clock_event_device *evt)

        val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);
        val &= ~NPCM7XX_Tx_OPER;
-
-       val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);
        val |= NPCM7XX_START_ONESHOT_Tx;
        writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0);