[v4,4/8] clk: sunxi-ng: v3s: add missing clock slices for MMC2 module clocks
diff mbox series

Message ID 20190713034634.44585-5-icenowy@aosc.io
State New
Headers show
Series
  • Support for Allwinner V3/S3L and Sochip S3
Related show

Commit Message

Icenowy Zheng July 13, 2019, 3:46 a.m. UTC
The MMC2 clock slices are currently not defined in V3s CCU driver, which
makes MMC2 not working.

Fix this issue.

Fixes: d0f11d14b0bc ("clk: sunxi-ng: add support for V3s CCU")
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
New patch in v4.

 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c | 3 +++
 1 file changed, 3 insertions(+)

Comments

Maxime Ripard July 20, 2019, 9:44 a.m. UTC | #1
On Sat, Jul 13, 2019 at 11:46:30AM +0800, Icenowy Zheng wrote:
> The MMC2 clock slices are currently not defined in V3s CCU driver, which
> makes MMC2 not working.
>
> Fix this issue.
>
> Fixes: d0f11d14b0bc ("clk: sunxi-ng: add support for V3s CCU")
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> ---
> New patch in v4.
>
>  drivers/clk/sunxi-ng/ccu-sun8i-v3s.c | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
> index 4eb68243e310..9c88015d4419 100644
> --- a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
> +++ b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
> @@ -513,6 +513,9 @@ static struct clk_hw_onecell_data sun8i_v3s_hw_clks = {
>  		[CLK_MMC1]		= &mmc1_clk.common.hw,
>  		[CLK_MMC1_SAMPLE]	= &mmc1_sample_clk.common.hw,
>  		[CLK_MMC1_OUTPUT]	= &mmc1_output_clk.common.hw,
> +		[CLK_MMC2]		= &mmc1_clk.common.hw,
> +		[CLK_MMC2_SAMPLE]	= &mmc1_sample_clk.common.hw,
> +		[CLK_MMC2_OUTPUT]	= &mmc1_output_clk.common.hw,

You're using the same structures than mmc1, I guess it's a copy and
paste mistake?

Maxime

--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
Icenowy Zheng July 20, 2019, 9:45 a.m. UTC | #2
于 2019年7月20日 GMT+08:00 下午5:44:49, Maxime Ripard <maxime.ripard@bootlin.com> 写到:
>On Sat, Jul 13, 2019 at 11:46:30AM +0800, Icenowy Zheng wrote:
>> The MMC2 clock slices are currently not defined in V3s CCU driver,
>which
>> makes MMC2 not working.
>>
>> Fix this issue.
>>
>> Fixes: d0f11d14b0bc ("clk: sunxi-ng: add support for V3s CCU")
>> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
>> ---
>> New patch in v4.
>>
>>  drivers/clk/sunxi-ng/ccu-sun8i-v3s.c | 3 +++
>>  1 file changed, 3 insertions(+)
>>
>> diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
>b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
>> index 4eb68243e310..9c88015d4419 100644
>> --- a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
>> +++ b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
>> @@ -513,6 +513,9 @@ static struct clk_hw_onecell_data
>sun8i_v3s_hw_clks = {
>>  		[CLK_MMC1]		= &mmc1_clk.common.hw,
>>  		[CLK_MMC1_SAMPLE]	= &mmc1_sample_clk.common.hw,
>>  		[CLK_MMC1_OUTPUT]	= &mmc1_output_clk.common.hw,
>> +		[CLK_MMC2]		= &mmc1_clk.common.hw,
>> +		[CLK_MMC2_SAMPLE]	= &mmc1_sample_clk.common.hw,
>> +		[CLK_MMC2_OUTPUT]	= &mmc1_output_clk.common.hw,
>
>You're using the same structures than mmc1, I guess it's a copy and
>paste mistake?

Yes.

>
>Maxime
>
>--
>Maxime Ripard, Bootlin
>Embedded Linux and Kernel engineering
>https://bootlin.com

Patch
diff mbox series

diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
index 4eb68243e310..9c88015d4419 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
@@ -513,6 +513,9 @@  static struct clk_hw_onecell_data sun8i_v3s_hw_clks = {
 		[CLK_MMC1]		= &mmc1_clk.common.hw,
 		[CLK_MMC1_SAMPLE]	= &mmc1_sample_clk.common.hw,
 		[CLK_MMC1_OUTPUT]	= &mmc1_output_clk.common.hw,
+		[CLK_MMC2]		= &mmc1_clk.common.hw,
+		[CLK_MMC2_SAMPLE]	= &mmc1_sample_clk.common.hw,
+		[CLK_MMC2_OUTPUT]	= &mmc1_output_clk.common.hw,
 		[CLK_CE]		= &ce_clk.common.hw,
 		[CLK_SPI0]		= &spi0_clk.common.hw,
 		[CLK_USB_PHY0]		= &usb_phy0_clk.common.hw,