From patchwork Fri Jul 12 11:17:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vasant Hegde X-Patchwork-Id: 1131307 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 45lVsb3tXNz9sBF for ; Fri, 12 Jul 2019 21:23:15 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.vnet.ibm.com Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 45lVsb2xQBzDr2q for ; Fri, 12 Jul 2019 21:23:15 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=none (mailfrom) smtp.mailfrom=linux.vnet.ibm.com (client-ip=148.163.158.5; helo=mx0a-001b2d01.pphosted.com; envelope-from=hegdevasant@linux.vnet.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.vnet.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 45lVmb600mzDqfC for ; Fri, 12 Jul 2019 21:18:55 +1000 (AEST) Received: from pps.filterd (m0098420.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x6CBGrGW158290 for ; Fri, 12 Jul 2019 07:18:53 -0400 Received: from e06smtp01.uk.ibm.com (e06smtp01.uk.ibm.com [195.75.94.97]) by mx0b-001b2d01.pphosted.com with ESMTP id 2tprra999k-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Fri, 12 Jul 2019 07:18:53 -0400 Received: from localhost by e06smtp01.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Fri, 12 Jul 2019 12:18:48 +0100 Received: from d06av22.portsmouth.uk.ibm.com (d06av22.portsmouth.uk.ibm.com [9.149.105.58]) by b06cxnps3074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x6CBIlGm55705700 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 12 Jul 2019 11:18:47 GMT Received: from d06av22.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 7DE814C046; Fri, 12 Jul 2019 11:18:47 +0000 (GMT) Received: from d06av22.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 577A04C040; Fri, 12 Jul 2019 11:18:45 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.199.176.57]) by d06av22.portsmouth.uk.ibm.com (Postfix) with ESMTP; Fri, 12 Jul 2019 11:18:45 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Fri, 12 Jul 2019 16:47:52 +0530 X-Mailer: git-send-email 2.14.3 In-Reply-To: <20190712111802.23560-1-hegdevasant@linux.vnet.ibm.com> References: <20190712111802.23560-1-hegdevasant@linux.vnet.ibm.com> X-TM-AS-GCONF: 00 x-cbid: 19071211-4275-0000-0000-0000034C7440 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19071211-4276-0000-0000-0000385C7E40 Message-Id: <20190712111802.23560-16-hegdevasant@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-07-12_03:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1907120122 Subject: [Skiboot] [PATCH v9 15/25] MPIPL: Add support to trigger MPIPL on BMC system X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: stewart@linux.vnet.ibm.com, mikey@neuling.org, hbathini@linux.vnet.ibm.com MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" On FSP based system we call 'attn' instruction. FSP detects attention and initiates memory preserving IPL. On BMC system we have to call SBE S0 interrupt to initiate memory preserving IPL. This patch adds support to call SBE S0 interrupt in assert path. Sequence : - S0 interrupt on secondary chip SBE - S0 interrupt on primary chip SBE Note that this is hooked to ipmi_terminate path. We have HDAT flag for MPIPL support. If MPIPL is not supported then we don't create 'ibm,opal/dump' node and we will fall back to existing termination flow. Finally we want to log error log to BMC before triggerring MPIPL. Hence this patch re-organizes ipmi_terminate() such that we call ipmi_log_terminate_event() before triggering MPIPL. Note: - At present we do not have a proper way to detect SBE is alive or not. So we wait for predefined time and then call normal reboot. Signed-off-by: Vasant Hegde --- hw/ipmi/ipmi-attn.c | 16 ++++++++++---- hw/sbe-p9.c | 63 +++++++++++++++++++++++++++++++++++++++++++++++++++++ include/sbe-p9.h | 10 +++++++++ 3 files changed, 85 insertions(+), 4 deletions(-) diff --git a/hw/ipmi/ipmi-attn.c b/hw/ipmi/ipmi-attn.c index c6c1c59b5..13e3932a9 100644 --- a/hw/ipmi/ipmi-attn.c +++ b/hw/ipmi/ipmi-attn.c @@ -1,4 +1,4 @@ -/* Copyright 2015 IBM Corp. +/* Copyright 2015-2019 IBM Corp. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -65,6 +66,16 @@ static void ipmi_log_terminate_event(const char *msg) void __attribute__((noreturn)) ipmi_terminate(const char *msg) { + /* Log eSEL event */ + if (ipmi_present()) + ipmi_log_terminate_event(msg); + + /* + * If mpipl is supported then trigger SBE interrupt + * to initiate mpipl + */ + p9_sbe_terminate(); + /* Terminate called before initializing IPMI (early abort) */ if (!ipmi_present()) { if (platform.cec_reboot) @@ -72,9 +83,6 @@ void __attribute__((noreturn)) ipmi_terminate(const char *msg) goto out; } - /* Log eSEL event */ - ipmi_log_terminate_event(msg); - /* Reboot call */ if (platform.cec_reboot) platform.cec_reboot(); diff --git a/hw/sbe-p9.c b/hw/sbe-p9.c index d3dd4bdb4..58a296c00 100644 --- a/hw/sbe-p9.c +++ b/hw/sbe-p9.c @@ -948,3 +948,66 @@ void p9_sbe_init(void) /* Initiate SBE timeout poller */ opal_add_poller(p9_sbe_timeout_poll, NULL); } + +/* Terminate and initiate MPIPL */ +void p9_sbe_terminate(void) +{ + uint32_t primary_chip = -1; + int rc; + u64 wait_tb; + struct proc_chip *chip; + + /* Return if MPIPL is not supported */ + if (!dt_find_by_path(opal_node, "dump")) + return; + + /* + * Send S0 interrupt to all SBE. Sequence: + * - S0 interrupt on secondary chip SBE + * - S0 interrupt on Primary chip SBE + */ + for_each_chip(chip) { + if (dt_has_node_property(chip->devnode, "primary", NULL)) { + primary_chip = chip->id; + continue; + } + + rc = xscom_write(chip->id, + SBE_CONTROL_REG_RW, SBE_CONTROL_REG_S0); + /* Initiate normal reboot */ + if (rc) { + prlog(PR_ERR, "Failed to write S0 interrupt [chip id = %x]\n", + chip->id); + return; + } + } + + /* Initiate normal reboot */ + if (primary_chip == -1) { + prlog(PR_ERR, "Primary chip ID not found.\n"); + return; + } + + rc = xscom_write(primary_chip, + SBE_CONTROL_REG_RW, SBE_CONTROL_REG_S0); + if (rc) { + prlog(PR_ERR, "Failed to write S0 interrupt [chip id = %x]\n", + primary_chip); + return; + } + + /* XXX We expect SBE to act on interrupt, quiesce the system and start + * MPIPL flow. Currently we do not have a way to detect SBE state. + * Hence wait for max time SBE takes to respond and then trigger + * normal reboot. + */ + prlog(PR_NOTICE, "Initiated MPIPL, waiting for SBE to respond...\n"); + wait_tb = mftb() + msecs_to_tb(SBE_CMD_TIMEOUT_MAX); + while (mftb() < wait_tb) { + cpu_relax(); + } + + prlog(PR_ERR, "SBE did not respond within timeout period (%d secs).\n", + SBE_CMD_TIMEOUT_MAX / 1000); + prlog(PR_ERR, "Falling back to normal reboot\n"); +} diff --git a/include/sbe-p9.h b/include/sbe-p9.h index 1191a94b4..32feb22fa 100644 --- a/include/sbe-p9.h +++ b/include/sbe-p9.h @@ -103,6 +103,13 @@ #define SBE_HOST_TIMER_EXPIRY PPC_BIT(14) #define SBE_HOST_RESPONSE_MASK (PPC_BITMASK(0, 4) | SBE_HOST_TIMER_EXPIRY) +/* SBE Control Register */ +#define SBE_CONTROL_REG_RW 0x00050008 + +/* SBE interrupt s0/s1 bits */ +#define SBE_CONTROL_REG_S0 PPC_BIT(14) +#define SBE_CONTROL_REG_S1 PPC_BIT(15) + /* SBE Target Type */ #define SBE_TARGET_TYPE_PROC 0x00 #define SBE_TARGET_TYPE_EX 0x01 @@ -243,4 +250,7 @@ extern void p9_sbe_update_timer_expiry(uint64_t new_target); /* Send skiboot relocated base address to SBE */ extern void p9_sbe_send_relocated_base(uint64_t reloc_base); +/* Terminate and trigger MPIPL */ +extern void p9_sbe_terminate(void); + #endif /* __SBE_P9_H */