[4/5] cpu/msr: add MSR_BBL_CR_CTL3 to IA32_silvermont_MSRs
diff mbox series

Message ID 20190712050822.21432-5-alex.hung@canonical.com
State Accepted
Headers show
Series
  • Updates atom MSRs in IA32_silvermont_MSRs
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Commit Message

Alex Hung July 12, 2019, 5:08 a.m. UTC
BIT definition is as below:

0	L2 Hardware Enabled (RO)
7:1	Reserved
8	L2 Enabled (R/W)
22:9	Reserved
23	L2 Not Present (RO)
63:24	Reserved

Signed-off-by: Alex Hung <alex.hung@canonical.com>
---
 src/cpu/msr/msr.c | 1 +
 1 file changed, 1 insertion(+)

Comments

Ivan Hu July 24, 2019, 8:03 a.m. UTC | #1
On 7/12/19 1:08 PM, Alex Hung wrote:
> BIT definition is as below:
> 
> 0	L2 Hardware Enabled (RO)
> 7:1	Reserved
> 8	L2 Enabled (R/W)
> 22:9	Reserved
> 23	L2 Not Present (RO)
> 63:24	Reserved
> 
> Signed-off-by: Alex Hung <alex.hung@canonical.com>
> ---
>   src/cpu/msr/msr.c | 1 +
>   1 file changed, 1 insertion(+)
> 
> diff --git a/src/cpu/msr/msr.c b/src/cpu/msr/msr.c
> index f08dac65..daa75d57 100644
> --- a/src/cpu/msr/msr.c
> +++ b/src/cpu/msr/msr.c
> @@ -482,6 +482,7 @@ static const msr_info IA32_atom_MSRs[] = {
>   
>   static const msr_info IA32_silvermont_MSRs[] = {
>   	{ "MSR_PMG_IO_CAPTURE_BASE",	0x000000e4,	0x000000000007ffffULL, NULL },
> +	{ "MSR_BBL_CR_CTL3",		0x0000011e,	0x0000000000800101ULL, NULL },
>   	{ "MSR_FEATURE_CONFIG",		0x0000013c,	0x0000000000000003ULL, NULL },
>   	{ "MSR_TEMPERATURE_TARGET",	0x000001a2,	0x000000003fff0000ULL, NULL },
>   	{ NULL,				0x00000000,	0, NULL },
> 

Acked-by: Ivan Hu <ivan.hu@canonical.com>
Colin Ian King July 24, 2019, 3:09 p.m. UTC | #2
On 12/07/2019 06:08, Alex Hung wrote:
> BIT definition is as below:
> 
> 0	L2 Hardware Enabled (RO)
> 7:1	Reserved
> 8	L2 Enabled (R/W)
> 22:9	Reserved
> 23	L2 Not Present (RO)
> 63:24	Reserved
> 
> Signed-off-by: Alex Hung <alex.hung@canonical.com>
> ---
>  src/cpu/msr/msr.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/src/cpu/msr/msr.c b/src/cpu/msr/msr.c
> index f08dac65..daa75d57 100644
> --- a/src/cpu/msr/msr.c
> +++ b/src/cpu/msr/msr.c
> @@ -482,6 +482,7 @@ static const msr_info IA32_atom_MSRs[] = {
>  
>  static const msr_info IA32_silvermont_MSRs[] = {
>  	{ "MSR_PMG_IO_CAPTURE_BASE",	0x000000e4,	0x000000000007ffffULL, NULL },
> +	{ "MSR_BBL_CR_CTL3",		0x0000011e,	0x0000000000800101ULL, NULL },
>  	{ "MSR_FEATURE_CONFIG",		0x0000013c,	0x0000000000000003ULL, NULL },
>  	{ "MSR_TEMPERATURE_TARGET",	0x000001a2,	0x000000003fff0000ULL, NULL },
>  	{ NULL,				0x00000000,	0, NULL },
> 

Acked-by: Colin Ian King <colin.king@canonical.com>

Patch
diff mbox series

diff --git a/src/cpu/msr/msr.c b/src/cpu/msr/msr.c
index f08dac65..daa75d57 100644
--- a/src/cpu/msr/msr.c
+++ b/src/cpu/msr/msr.c
@@ -482,6 +482,7 @@  static const msr_info IA32_atom_MSRs[] = {
 
 static const msr_info IA32_silvermont_MSRs[] = {
 	{ "MSR_PMG_IO_CAPTURE_BASE",	0x000000e4,	0x000000000007ffffULL, NULL },
+	{ "MSR_BBL_CR_CTL3",		0x0000011e,	0x0000000000800101ULL, NULL },
 	{ "MSR_FEATURE_CONFIG",		0x0000013c,	0x0000000000000003ULL, NULL },
 	{ "MSR_TEMPERATURE_TARGET",	0x000001a2,	0x000000003fff0000ULL, NULL },
 	{ NULL,				0x00000000,	0, NULL },