[2/3] cpu/msr: add MISC_ENABLE MSR to IA32_atom_MSRs
diff mbox series

Message ID 20190711175122.31499-3-alex.hung@canonical.com
State Accepted
Headers show
Series
  • Updates atom MSRs in IA32_atom_MSRs
Related show

Commit Message

Alex Hung July 11, 2019, 5:51 p.m. UTC
MISC_ENABLE in atom has more features than the one defined in
architectural MSRs (IA32_MSRs)

Signed-off-by: Alex Hung <alex.hung@canonical.com>
---
 src/cpu/msr/msr.c | 1 +
 1 file changed, 1 insertion(+)

Comments

Ivan Hu July 24, 2019, 8:01 a.m. UTC | #1
On 7/12/19 1:51 AM, Alex Hung wrote:
> MISC_ENABLE in atom has more features than the one defined in
> architectural MSRs (IA32_MSRs)
> 
> Signed-off-by: Alex Hung <alex.hung@canonical.com>
> ---
>   src/cpu/msr/msr.c | 1 +
>   1 file changed, 1 insertion(+)
> 
> diff --git a/src/cpu/msr/msr.c b/src/cpu/msr/msr.c
> index 1d5ed63f..7bcaf0b6 100644
> --- a/src/cpu/msr/msr.c
> +++ b/src/cpu/msr/msr.c
> @@ -476,6 +476,7 @@ static const msr_info IA32_atom_MSRs[] = {
>   	{ "MSR_FSB_FREQ",		0x000000cd,	0x0000000000000007ULL, NULL },
>   	{ "MSR_BBL_CR_CTL3",		0x0000011e,	0x0000000000800101ULL, NULL },
>   	{ "MSR_THERM2_CTL",		0x0000019d,	0x0000000000010000ULL, NULL },
> +	{ "MISC_ENABLE",		0x000001a0,	0x0000000400d53c89ULL, NULL },
>   	{ "MC0_CTL",			0x00000400,	0xffffffffffffffffULL, NULL },
>   	{ "MC0_STATUS",			0x00000401,	0xffffffffffffffffULL, NULL },
>   	{ "MC0_ADDR",			0x00000402,	0xffffffffffffffffULL, NULL },
> 

Acked-by: Ivan Hu <ivan.hu@canonical.com>
Colin King July 24, 2019, 3:10 p.m. UTC | #2
On 11/07/2019 18:51, Alex Hung wrote:
> MISC_ENABLE in atom has more features than the one defined in
> architectural MSRs (IA32_MSRs)
> 
> Signed-off-by: Alex Hung <alex.hung@canonical.com>
> ---
>  src/cpu/msr/msr.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/src/cpu/msr/msr.c b/src/cpu/msr/msr.c
> index 1d5ed63f..7bcaf0b6 100644
> --- a/src/cpu/msr/msr.c
> +++ b/src/cpu/msr/msr.c
> @@ -476,6 +476,7 @@ static const msr_info IA32_atom_MSRs[] = {
>  	{ "MSR_FSB_FREQ",		0x000000cd,	0x0000000000000007ULL, NULL },
>  	{ "MSR_BBL_CR_CTL3",		0x0000011e,	0x0000000000800101ULL, NULL },
>  	{ "MSR_THERM2_CTL",		0x0000019d,	0x0000000000010000ULL, NULL },
> +	{ "MISC_ENABLE",		0x000001a0,	0x0000000400d53c89ULL, NULL },
>  	{ "MC0_CTL",			0x00000400,	0xffffffffffffffffULL, NULL },
>  	{ "MC0_STATUS",			0x00000401,	0xffffffffffffffffULL, NULL },
>  	{ "MC0_ADDR",			0x00000402,	0xffffffffffffffffULL, NULL },
> 
Acked-by: Colin Ian King <colin.king@canonical.com>

Patch
diff mbox series

diff --git a/src/cpu/msr/msr.c b/src/cpu/msr/msr.c
index 1d5ed63f..7bcaf0b6 100644
--- a/src/cpu/msr/msr.c
+++ b/src/cpu/msr/msr.c
@@ -476,6 +476,7 @@  static const msr_info IA32_atom_MSRs[] = {
 	{ "MSR_FSB_FREQ",		0x000000cd,	0x0000000000000007ULL, NULL },
 	{ "MSR_BBL_CR_CTL3",		0x0000011e,	0x0000000000800101ULL, NULL },
 	{ "MSR_THERM2_CTL",		0x0000019d,	0x0000000000010000ULL, NULL },
+	{ "MISC_ENABLE",		0x000001a0,	0x0000000400d53c89ULL, NULL },
 	{ "MC0_CTL",			0x00000400,	0xffffffffffffffffULL, NULL },
 	{ "MC0_STATUS",			0x00000401,	0xffffffffffffffffULL, NULL },
 	{ "MC0_ADDR",			0x00000402,	0xffffffffffffffffULL, NULL },