[09/10] cpu/msr: update fields for MTRR_DEF_TYPE MSR
diff mbox series

Message ID 20190711174635.770-10-alex.hung@canonical.com
State Accepted
Headers show
Series
  • Updates architectural MSRs in IA32_MSRs
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Commit Message

Alex Hung July 11, 2019, 5:46 p.m. UTC
BIT definition is as below:

2:0	Default Memory Type
9:3	Reserved
10	Fixed Range MTRR Enable
11	MTRR Enable
63:12	Reserved

Signed-off-by: Alex Hung <alex.hung@canonical.com>
---
 src/cpu/msr/msr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Ivan Hu July 24, 2019, 7:49 a.m. UTC | #1
On 7/12/19 1:46 AM, Alex Hung wrote:
> BIT definition is as below:
> 
> 2:0	Default Memory Type
> 9:3	Reserved
> 10	Fixed Range MTRR Enable
> 11	MTRR Enable
> 63:12	Reserved
> 
> Signed-off-by: Alex Hung <alex.hung@canonical.com>
> ---
>   src/cpu/msr/msr.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/src/cpu/msr/msr.c b/src/cpu/msr/msr.c
> index 30c94e93..aa2e87dd 100644
> --- a/src/cpu/msr/msr.c
> +++ b/src/cpu/msr/msr.c
> @@ -434,7 +434,7 @@ static const msr_info IA32_MSRs[] = {
>   	{ "MC29_CTL2",			0x0000029d,	0x0000000040007fffULL, NULL },
>   	{ "MC30_CTL2",			0x0000029e,	0x0000000040007fffULL, NULL },
>   	{ "MC31_CTL2",			0x0000029f,	0x0000000040007fffULL, NULL },
> -	{ "MTRR_DEF_TYPE",		0x000002ff,	0x0000000000000c0fULL, NULL },
> +	{ "MTRR_DEF_TYPE",		0x000002ff,	0x0000000000000c07ULL, NULL },
>   	{ "PEBS_ENABLE",		0x000003f1,	0x0000000000000001ULL, NULL },
>   	{ "VMX_BASIC",			0x00000480,	0xffffffffffffffffULL, NULL },
>   	{ "VMX_PINPASED_CTLS",		0x00000481,	0xffffffffffffffffULL, NULL },
> 

Acked-by: Ivan Hu <ivan.hu@canonical.com>
Colin Ian King July 24, 2019, 3:06 p.m. UTC | #2
On 11/07/2019 18:46, Alex Hung wrote:
> BIT definition is as below:
> 
> 2:0	Default Memory Type
> 9:3	Reserved
> 10	Fixed Range MTRR Enable
> 11	MTRR Enable
> 63:12	Reserved
> 
> Signed-off-by: Alex Hung <alex.hung@canonical.com>
> ---
>  src/cpu/msr/msr.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/src/cpu/msr/msr.c b/src/cpu/msr/msr.c
> index 30c94e93..aa2e87dd 100644
> --- a/src/cpu/msr/msr.c
> +++ b/src/cpu/msr/msr.c
> @@ -434,7 +434,7 @@ static const msr_info IA32_MSRs[] = {
>  	{ "MC29_CTL2",			0x0000029d,	0x0000000040007fffULL, NULL },
>  	{ "MC30_CTL2",			0x0000029e,	0x0000000040007fffULL, NULL },
>  	{ "MC31_CTL2",			0x0000029f,	0x0000000040007fffULL, NULL },
> -	{ "MTRR_DEF_TYPE",		0x000002ff,	0x0000000000000c0fULL, NULL },
> +	{ "MTRR_DEF_TYPE",		0x000002ff,	0x0000000000000c07ULL, NULL },
>  	{ "PEBS_ENABLE",		0x000003f1,	0x0000000000000001ULL, NULL },
>  	{ "VMX_BASIC",			0x00000480,	0xffffffffffffffffULL, NULL },
>  	{ "VMX_PINPASED_CTLS",		0x00000481,	0xffffffffffffffffULL, NULL },
> 
Acked-by: Colin Ian King <colin.king@canonical.com>

Patch
diff mbox series

diff --git a/src/cpu/msr/msr.c b/src/cpu/msr/msr.c
index 30c94e93..aa2e87dd 100644
--- a/src/cpu/msr/msr.c
+++ b/src/cpu/msr/msr.c
@@ -434,7 +434,7 @@  static const msr_info IA32_MSRs[] = {
 	{ "MC29_CTL2",			0x0000029d,	0x0000000040007fffULL, NULL },
 	{ "MC30_CTL2",			0x0000029e,	0x0000000040007fffULL, NULL },
 	{ "MC31_CTL2",			0x0000029f,	0x0000000040007fffULL, NULL },
-	{ "MTRR_DEF_TYPE",		0x000002ff,	0x0000000000000c0fULL, NULL },
+	{ "MTRR_DEF_TYPE",		0x000002ff,	0x0000000000000c07ULL, NULL },
 	{ "PEBS_ENABLE",		0x000003f1,	0x0000000000000001ULL, NULL },
 	{ "VMX_BASIC",			0x00000480,	0xffffffffffffffffULL, NULL },
 	{ "VMX_PINPASED_CTLS",		0x00000481,	0xffffffffffffffffULL, NULL },