[05/10] cpu/msr: update MTRRCAP MSR register
diff mbox series

Message ID 20190711174635.770-6-alex.hung@canonical.com
State Accepted
Headers show
Series
  • Updates architectural MSRs in IA32_MSRs
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Commit Message

Alex Hung July 11, 2019, 5:46 p.m. UTC
BIT9 is reserved, and BIT12 is "PRMRR supported when set".

Signed-off-by: Alex Hung <alex.hung@canonical.com>
---
 src/cpu/msr/msr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Ivan Hu July 24, 2019, 7:45 a.m. UTC | #1
On 7/12/19 1:46 AM, Alex Hung wrote:
> BIT9 is reserved, and BIT12 is "PRMRR supported when set".
> 
> Signed-off-by: Alex Hung <alex.hung@canonical.com>
> ---
>   src/cpu/msr/msr.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/src/cpu/msr/msr.c b/src/cpu/msr/msr.c
> index 9f94eee4..6e28bc1c 100644
> --- a/src/cpu/msr/msr.c
> +++ b/src/cpu/msr/msr.c
> @@ -348,7 +348,7 @@ static const msr_info IA32_MSRs[] = {
>   	{ "TSC_ADJUST",		0x0000003b,	0xffffffffffffffffULL, NULL },
>   	{ "BIOS_SIGN_ID",		0x0000008b,	0xffffffff00000000ULL, NULL },
>   	{ "SMM_MONITOR_CTL",            0x0000009b,     0x00000000fffff005ULL, NULL },
> -	{ "MTRRCAP",			0x000000fe,	0x0000000000000fffULL, NULL },
> +	{ "MTRRCAP",			0x000000fe,	0x0000000000001dffULL, NULL },
>   	/*
>   	 * LP#1582005 - Do not check sysenter MSRs, they will be different on
>   	 * each CPU, so checking them across CPUs is incorrect
> 

Acked-by: Ivan Hu <ivan.hu@canonical.com>
Colin Ian King July 24, 2019, 3:05 p.m. UTC | #2
On 11/07/2019 18:46, Alex Hung wrote:
> BIT9 is reserved, and BIT12 is "PRMRR supported when set".
> 
> Signed-off-by: Alex Hung <alex.hung@canonical.com>
> ---
>  src/cpu/msr/msr.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/src/cpu/msr/msr.c b/src/cpu/msr/msr.c
> index 9f94eee4..6e28bc1c 100644
> --- a/src/cpu/msr/msr.c
> +++ b/src/cpu/msr/msr.c
> @@ -348,7 +348,7 @@ static const msr_info IA32_MSRs[] = {
>  	{ "TSC_ADJUST",		0x0000003b,	0xffffffffffffffffULL, NULL },
>  	{ "BIOS_SIGN_ID",		0x0000008b,	0xffffffff00000000ULL, NULL },
>  	{ "SMM_MONITOR_CTL",            0x0000009b,     0x00000000fffff005ULL, NULL },
> -	{ "MTRRCAP",			0x000000fe,	0x0000000000000fffULL, NULL },
> +	{ "MTRRCAP",			0x000000fe,	0x0000000000001dffULL, NULL },
>  	/*
>  	 * LP#1582005 - Do not check sysenter MSRs, they will be different on
>  	 * each CPU, so checking them across CPUs is incorrect
> 
Acked-by: Colin Ian King <colin.king@canonical.com>

Patch
diff mbox series

diff --git a/src/cpu/msr/msr.c b/src/cpu/msr/msr.c
index 9f94eee4..6e28bc1c 100644
--- a/src/cpu/msr/msr.c
+++ b/src/cpu/msr/msr.c
@@ -348,7 +348,7 @@  static const msr_info IA32_MSRs[] = {
 	{ "TSC_ADJUST",		0x0000003b,	0xffffffffffffffffULL, NULL },
 	{ "BIOS_SIGN_ID",		0x0000008b,	0xffffffff00000000ULL, NULL },
 	{ "SMM_MONITOR_CTL",            0x0000009b,     0x00000000fffff005ULL, NULL },
-	{ "MTRRCAP",			0x000000fe,	0x0000000000000fffULL, NULL },
+	{ "MTRRCAP",			0x000000fe,	0x0000000000001dffULL, NULL },
 	/*
 	 * LP#1582005 - Do not check sysenter MSRs, they will be different on
 	 * each CPU, so checking them across CPUs is incorrect