[02/10] cpu/msr: check SGX & LMCE in IA32_FEATURE_CONTROL (3ah)
diff mbox series

Message ID 20190711174635.770-3-alex.hung@canonical.com
State Accepted
Headers show
Series
  • Updates architectural MSRs in IA32_MSRs
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Commit Message

Alex Hung July 11, 2019, 5:46 p.m. UTC
This includes SGX Launch Control Enable (BIT17), SGX Global Enable
(BIT18) and LMCE On (BIT20)

Signed-off-by: Alex Hung <alex.hung@canonical.com>
---
 src/cpu/msr/msr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Ivan Hu July 24, 2019, 7:21 a.m. UTC | #1
On 7/12/19 1:46 AM, Alex Hung wrote:
> This includes SGX Launch Control Enable (BIT17), SGX Global Enable
> (BIT18) and LMCE On (BIT20)
> 
> Signed-off-by: Alex Hung <alex.hung@canonical.com>
> ---
>   src/cpu/msr/msr.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/src/cpu/msr/msr.c b/src/cpu/msr/msr.c
> index a29e7cde..8972a161 100644
> --- a/src/cpu/msr/msr.c
> +++ b/src/cpu/msr/msr.c
> @@ -344,7 +344,7 @@ static const msr_info IA32_MSRs[] = {
>   	//{ "TIME_STAMP_COUNTER",	0x00000010,	0xffffffffffffffffULL, NULL },
>   	{ "PLATFORM_ID",		0x00000017,	0x001c000000000000ULL, NULL },
>   	{ "APIC_BASE",			0x0000001b,	0xfffffffffffffeffULL, NULL },
> -	{ "FEATURE_CONTROL",		0x0000003a,	0x000000000000ff07ULL, NULL },
> +	{ "FEATURE_CONTROL",		0x0000003a,	0x000000000016ff07ULL, NULL },
>   	{ "BIOS_SIGN_ID",		0x0000008b,	0xffffffff00000000ULL, NULL },
>   	{ "MTRRCAP",			0x000000fe,	0x0000000000000fffULL, NULL },
>   	/*
> 

Acked-by: Ivan Hu <ivan.hu@canonical.com>
Colin Ian King July 24, 2019, 3:03 p.m. UTC | #2
On 11/07/2019 18:46, Alex Hung wrote:
> This includes SGX Launch Control Enable (BIT17), SGX Global Enable
> (BIT18) and LMCE On (BIT20)
> 
> Signed-off-by: Alex Hung <alex.hung@canonical.com>
> ---
>  src/cpu/msr/msr.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/src/cpu/msr/msr.c b/src/cpu/msr/msr.c
> index a29e7cde..8972a161 100644
> --- a/src/cpu/msr/msr.c
> +++ b/src/cpu/msr/msr.c
> @@ -344,7 +344,7 @@ static const msr_info IA32_MSRs[] = {
>  	//{ "TIME_STAMP_COUNTER",	0x00000010,	0xffffffffffffffffULL, NULL },
>  	{ "PLATFORM_ID",		0x00000017,	0x001c000000000000ULL, NULL },
>  	{ "APIC_BASE",			0x0000001b,	0xfffffffffffffeffULL, NULL },
> -	{ "FEATURE_CONTROL",		0x0000003a,	0x000000000000ff07ULL, NULL },
> +	{ "FEATURE_CONTROL",		0x0000003a,	0x000000000016ff07ULL, NULL },
>  	{ "BIOS_SIGN_ID",		0x0000008b,	0xffffffff00000000ULL, NULL },
>  	{ "MTRRCAP",			0x000000fe,	0x0000000000000fffULL, NULL },
>  	/*
> 
Acked-by: Colin Ian King <colin.king@canonical.com>

Patch
diff mbox series

diff --git a/src/cpu/msr/msr.c b/src/cpu/msr/msr.c
index a29e7cde..8972a161 100644
--- a/src/cpu/msr/msr.c
+++ b/src/cpu/msr/msr.c
@@ -344,7 +344,7 @@  static const msr_info IA32_MSRs[] = {
 	//{ "TIME_STAMP_COUNTER",	0x00000010,	0xffffffffffffffffULL, NULL },
 	{ "PLATFORM_ID",		0x00000017,	0x001c000000000000ULL, NULL },
 	{ "APIC_BASE",			0x0000001b,	0xfffffffffffffeffULL, NULL },
-	{ "FEATURE_CONTROL",		0x0000003a,	0x000000000000ff07ULL, NULL },
+	{ "FEATURE_CONTROL",		0x0000003a,	0x000000000016ff07ULL, NULL },
 	{ "BIOS_SIGN_ID",		0x0000008b,	0xffffffff00000000ULL, NULL },
 	{ "MTRRCAP",			0x000000fe,	0x0000000000000fffULL, NULL },
 	/*