From patchwork Tue Jul 9 13:09:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qii Wang X-Patchwork-Id: 1129774 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=mediatek.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45jjN61ht3z9sNC for ; Tue, 9 Jul 2019 23:09:58 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726523AbfGINJy (ORCPT ); Tue, 9 Jul 2019 09:09:54 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:22880 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726345AbfGINJx (ORCPT ); Tue, 9 Jul 2019 09:09:53 -0400 X-UUID: 040cb6db70d6486b9edf9840134d1ed8-20190709 X-UUID: 040cb6db70d6486b9edf9840134d1ed8-20190709 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 696691753; Tue, 09 Jul 2019 21:09:46 +0800 Received: from mtkcas09.mediatek.inc (172.21.101.178) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 9 Jul 2019 21:09:45 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Tue, 9 Jul 2019 21:09:45 +0800 From: Qii Wang To: CC: , , , , , , , , , , , , Subject: [PATCH v3 1/2] dt-bindings: i3c: Document MediaTek I3C master bindings Date: Tue, 9 Jul 2019 21:09:21 +0800 Message-ID: <1562677762-24067-2-git-send-email-qii.wang@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1562677762-24067-1-git-send-email-qii.wang@mediatek.com> References: <1562677762-24067-1-git-send-email-qii.wang@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Document MediaTek I3C master DT bindings. Signed-off-by: Qii Wang --- .../devicetree/bindings/i3c/mtk,i3c-master.txt | 48 ++++++++++++++++++++ 1 file changed, 48 insertions(+) create mode 100644 Documentation/devicetree/bindings/i3c/mtk,i3c-master.txt diff --git a/Documentation/devicetree/bindings/i3c/mtk,i3c-master.txt b/Documentation/devicetree/bindings/i3c/mtk,i3c-master.txt new file mode 100644 index 0000000..d32eda6 --- /dev/null +++ b/Documentation/devicetree/bindings/i3c/mtk,i3c-master.txt @@ -0,0 +1,48 @@ +Bindings for MediaTek I3C master block +===================================== + +Required properties: +-------------------- +- compatible: shall be "mediatek,i3c-master" +- reg: physical base address of the controller and apdma base, length of + memory mapped region. +- reg-names: shall be "main" for master controller and "dma" for apdma. +- interrupts: the interrupt line connected to this I3C master. +- clocks: shall reference the i3c and apdma clocks. +- clock-names: shall include "main" and "dma". + +Mandatory properties defined by the generic binding (see +Documentation/devicetree/bindings/i3c/i3c.txt for more details): + +- #address-cells: shall be set to 3 +- #size-cells: shall be set to 0 + +Optional properties defined by the generic binding (see +Documentation/devicetree/bindings/i3c/i3c.txt for more details): + +- i2c-scl-hz +- i3c-scl-hz + +I3C device connected on the bus follow the generic description (see +Documentation/devicetree/bindings/i3c/i3c.txt for more details). + +Example: + + i3c0: i3c@1100d000 { + compatible = "mediatek,i3c-master"; + reg = <0x1100d000 0x1000>, + <0x11000300 0x80>; + reg-names = "main", "dma"; + interrupts = ; + clocks = <&infracfg CLK_INFRA_I3C0>, + <&infracfg CLK_INFRA_AP_DMA>; + clock-names = "main", "dma"; + #address-cells = <3>; + #size-cells = <0>; + i2c-scl-hz = <100000>; + + nunchuk: nunchuk@52 { + compatible = "nintendo,nunchuk"; + reg = <0x52 0x0 0x10>; + }; + };