From patchwork Tue Jul 9 08:41:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerry-ch Chen X-Patchwork-Id: 1129639 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=mediatek.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45jbQs4ZCpz9sNF for ; Tue, 9 Jul 2019 18:41:57 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726529AbfGIIl5 (ORCPT ); Tue, 9 Jul 2019 04:41:57 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:44272 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726031AbfGIIl4 (ORCPT ); Tue, 9 Jul 2019 04:41:56 -0400 X-UUID: 9c75774d71ca454ebddc8c7453180b67-20190709 X-UUID: 9c75774d71ca454ebddc8c7453180b67-20190709 Received: from mtkmrs01.mediatek.inc [(172.21.131.159)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 358703888; Tue, 09 Jul 2019 16:41:52 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs01n2.mediatek.inc (172.21.101.79) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 9 Jul 2019 16:41:50 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Tue, 9 Jul 2019 16:41:51 +0800 From: Jerry-ch Chen To: , , , , CC: , , , , , , , , , , , , , , , , , Jerry-ch Chen Subject: [RFC PATCH V2 1/4] dt-bindings: mt8183: Added FD dt-bindings Date: Tue, 9 Jul 2019 16:41:09 +0800 Message-ID: <1562661672-22439-2-git-send-email-Jerry-Ch.chen@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1562661672-22439-1-git-send-email-Jerry-Ch.chen@mediatek.com> References: <1562661672-22439-1-git-send-email-Jerry-Ch.chen@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 4C8DA7255699FBF35C58CED08BC665ECFBEF24395DB42C8AFB9769DC6D4C5F972000:8 X-MTK: N Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Jerry-ch Chen This patch adds DT binding documentation for the Face Detection (FD) unit of the Mediatek's mt8183 SoC. Signed-off-by: Jerry-ch Chen --- .../bindings/media/mediatek,mt8183-fd.txt | 33 ++++++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/mediatek,mt8183-fd.txt diff --git a/Documentation/devicetree/bindings/media/mediatek,mt8183-fd.txt b/Documentation/devicetree/bindings/media/mediatek,mt8183-fd.txt new file mode 100644 index 0000000..0837223 --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek,mt8183-fd.txt @@ -0,0 +1,33 @@ +* Mediatek Face Detection Unit (FD) + +Face Detection (FD) unit is a typical memory-to-memory HW device. +It provides hardware accelerated face detection function, and it +is able to detect different poses of faces. FD will writre result +of detected face into memory as output. + +Required properties: +- compatible: "mediatek,mt8183-fd" +- mediatek,scp : the node of system control processor (SCP), see + Documentation/devicetree/bindings/remoteproc/mtk,scp.txt for details. +- iommus: should point to the 3 entries: M4U_PORT_CAM_FDVT_RP, + M4U_PORT_CAM_FDVT_WR and M4U_PORT_CAM_FDVT_RB. (Please see + Documentation/devicetree/bindings/iommu/mediatek,iommu.txt for details.) +- reg: Physical base address and length of the register space. +- interrupts: interrupt number to the cpu. +- clocks : must contain the FDVT clock, see + Documentation/devicetree/bindings/clock/clock-bindings.txt for details. +- clock-names: must be "fd". + +Example: + fd: fd@1502b000 { + compatible = "mediatek,mt8183-fd"; + mediatek,scp = <&scp>; + iommus = <&iommu M4U_PORT_CAM_FDVT_RP>, + <&iommu M4U_PORT_CAM_FDVT_WR>, + <&iommu M4U_PORT_CAM_FDVT_RB>; + reg = <0 0x1502b000 0 0x1000>; + interrupts = ; + clocks = <&imgsys CLK_IMG_FDVT>; + clock-names = "fd"; + }; +