[U-Boot,V2,51/51] imx: add i.MX8MN DDR4 board support
diff mbox series

Message ID 20190708015333.20411-52-peng.fan@nxp.com
State Rejected
Delegated to: Stefano Babic
Headers show
Series
  • Support i.MX8MM/N
Related show

Commit Message

Peng Fan July 8, 2019, 1:40 a.m. UTC
Support pinctrl/clk/sdhc, include ddr4 timing data.

Log:
U-Boot SPL 2019.07-rc4-00310-geff364e1d0 (Jul 02 2019 - 09:47:06 +0800)
DDRINFO: start DRAM init
DDRINFO:ddrphy calibration done
DDRINFO: ddrmix config done
Normal Boot
Trying to boot from BOOTROM
image offset 0x8000, pagesize 0x200, ivt offset 0x0

U-Boot 2019.07-rc4-00310-geff364e1d0 (Jul 02 2019 - 09:47:06 +0800)

CPU:   Freescale i.MX8MNano rev1.0 at 1000 MHz
Reset cause: POR
Model: FSL i.MX8MM EVK board
DRAM:  2 GiB
MMC:   FSL_SDHC: 1, FSL_SDHC: 2
In:    serial
Out:   serial
Err:   serial
Net:   No ethernet found.
Hit any key to stop autoboot:  0

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/dts/Makefile                    |    3 +-
 arch/arm/dts/imx8mm-evk.dts              |    6 +-
 arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi |   92 +++
 arch/arm/dts/imx8mn-ddr4-evk.dts         |  221 ++++++
 arch/arm/mach-imx/imx8m/Kconfig          |    7 +
 board/freescale/imx8mn_evk/Kconfig       |   14 +
 board/freescale/imx8mn_evk/MAINTAINERS   |    6 +
 board/freescale/imx8mn_evk/Makefile      |   12 +
 board/freescale/imx8mn_evk/ddr4_timing.c | 1213 ++++++++++++++++++++++++++++++
 board/freescale/imx8mn_evk/imx8mn_evk.c  |   85 +++
 board/freescale/imx8mn_evk/spl.c         |   90 +++
 configs/imx8mn_ddr4_evk_defconfig        |   53 ++
 include/configs/imx8mn_evk.h             |  198 +++++
 13 files changed, 1996 insertions(+), 4 deletions(-)
 create mode 100644 arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
 create mode 100644 arch/arm/dts/imx8mn-ddr4-evk.dts
 create mode 100644 board/freescale/imx8mn_evk/Kconfig
 create mode 100644 board/freescale/imx8mn_evk/MAINTAINERS
 create mode 100644 board/freescale/imx8mn_evk/Makefile
 create mode 100644 board/freescale/imx8mn_evk/ddr4_timing.c
 create mode 100644 board/freescale/imx8mn_evk/imx8mn_evk.c
 create mode 100644 board/freescale/imx8mn_evk/spl.c
 create mode 100644 configs/imx8mn_ddr4_evk_defconfig
 create mode 100644 include/configs/imx8mn_evk.h

Comments

Lukasz Majewski July 10, 2019, 8:34 a.m. UTC | #1
Hi Peng,

> Support pinctrl/clk/sdhc, include ddr4 timing data.
> 
> Log:
> U-Boot SPL 2019.07-rc4-00310-geff364e1d0 (Jul 02 2019 - 09:47:06
> +0800) DDRINFO: start DRAM init
> DDRINFO:ddrphy calibration done
> DDRINFO: ddrmix config done
> Normal Boot
> Trying to boot from BOOTROM
> image offset 0x8000, pagesize 0x200, ivt offset 0x0
> 
> U-Boot 2019.07-rc4-00310-geff364e1d0 (Jul 02 2019 - 09:47:06 +0800)
> 
> CPU:   Freescale i.MX8MNano rev1.0 at 1000 MHz
> Reset cause: POR
> Model: FSL i.MX8MM EVK board
> DRAM:  2 GiB
> MMC:   FSL_SDHC: 1, FSL_SDHC: 2
> In:    serial
> Out:   serial
> Err:   serial
> Net:   No ethernet found.
> Hit any key to stop autoboot:  0
> 
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
>  arch/arm/dts/Makefile                    |    3 +-
>  arch/arm/dts/imx8mm-evk.dts              |    6 +-
>  arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi |   92 +++
>  arch/arm/dts/imx8mn-ddr4-evk.dts         |  221 ++++++
>  arch/arm/mach-imx/imx8m/Kconfig          |    7 +
>  board/freescale/imx8mn_evk/Kconfig       |   14 +
>  board/freescale/imx8mn_evk/MAINTAINERS   |    6 +
>  board/freescale/imx8mn_evk/Makefile      |   12 +
>  board/freescale/imx8mn_evk/ddr4_timing.c | 1213
> ++++++++++++++++++++++++++++++
> board/freescale/imx8mn_evk/imx8mn_evk.c  |   85 +++
> board/freescale/imx8mn_evk/spl.c         |   90 +++
> configs/imx8mn_ddr4_evk_defconfig        |   53 ++
> include/configs/imx8mn_evk.h             |  198 +++++ 13 files
> changed, 1996 insertions(+), 4 deletions(-) create mode 100644
> arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi create mode 100644
> arch/arm/dts/imx8mn-ddr4-evk.dts create mode 100644
> board/freescale/imx8mn_evk/Kconfig create mode 100644
> board/freescale/imx8mn_evk/MAINTAINERS create mode 100644
> board/freescale/imx8mn_evk/Makefile create mode 100644
> board/freescale/imx8mn_evk/ddr4_timing.c create mode 100644
> board/freescale/imx8mn_evk/imx8mn_evk.c create mode 100644
> board/freescale/imx8mn_evk/spl.c create mode 100644
> configs/imx8mn_ddr4_evk_defconfig create mode 100644
> include/configs/imx8mn_evk.h
> 
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 8b7822cd99..e262880b79 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -617,7 +617,8 @@ dtb-$(CONFIG_ARCH_IMX8) += \
>  	fsl-imx8qxp-mek.dtb
>  
>  dtb-$(CONFIG_ARCH_IMX8M) += fsl-imx8mq-evk.dtb \
> -	imx8mm-evk.dtb
> +	imx8mm-evk.dtb \
> +	imx8mn-ddr4-evk.dtb
>  
>  dtb-$(CONFIG_RCAR_GEN2) += \
>  	r8a7790-lager-u-boot.dtb \
> diff --git a/arch/arm/dts/imx8mm-evk.dts b/arch/arm/dts/imx8mm-evk.dts
> index 2d5d89475b..1e8b10a965 100644
> --- a/arch/arm/dts/imx8mm-evk.dts
> +++ b/arch/arm/dts/imx8mm-evk.dts
> @@ -191,7 +191,7 @@
>  			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5
> 0x1d0 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d0
>  			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7
> 0x1d0
> -			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE
> 		0x190
> +
> MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x190

Those changes looks identical. Why do you need to change those lines?
(Wrong formatting) ?

>  		>;  
>  	};
>  
> @@ -207,7 +207,7 @@
>  			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5
> 0x1d4 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d4
>  			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7
> 0x1d4
> -			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE
> 		0x194
> +
> MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x194
>  		>;  
>  	};
>  
> @@ -223,7 +223,7 @@
>  			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5
> 0x1d6 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d6
>  			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7
> 0x1d6
> -			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE
> 		0x196
> +
> MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x196
>  		>;  
>  	};
>  
> diff --git a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
> b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi new file mode 100644
> index 0000000000..8d61597e0c
> --- /dev/null
> +++ b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
> @@ -0,0 +1,92 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2019 NXP
> + */
> +
> +&{/soc@0} {
> +	u-boot,dm-pre-reloc;
> +	u-boot,dm-spl;
> +};
> +
> +&clk {
> +	u-boot,dm-spl;
> +	u-boot,dm-pre-reloc;
> +};
> +
> +&osc_24m {
> +	u-boot,dm-spl;
> +	u-boot,dm-pre-reloc;
> +};
> +
> +&aips1 {
> +	u-boot,dm-spl;
> +	u-boot,dm-pre-reloc;
> +};
> +
> +&aips2 {
> +	u-boot,dm-spl;
> +};
> +
> +&aips3 {
> +	u-boot,dm-spl;
> +};
> +
> +&iomuxc {
> +	u-boot,dm-spl;
> +};
> +
> +&pinctrl_reg_usdhc2_vmmc {
> +	u-boot,dm-spl;
> +};
> +
> +&pinctrl_uart2 {
> +	u-boot,dm-spl;
> +};
> +
> +&pinctrl_usdhc2_gpio {
> +	u-boot,dm-spl;
> +};
> +
> +&pinctrl_usdhc2 {
> +	u-boot,dm-spl;
> +};
> +
> +&pinctrl_usdhc3 {
> +	u-boot,dm-spl;
> +};
> +
> +&gpio1 {
> +	u-boot,dm-spl;
> +};
> +
> +&gpio2 {
> +	u-boot,dm-spl;
> +};
> +
> +&gpio3 {
> +	u-boot,dm-spl;
> +};
> +
> +&gpio4 {
> +	u-boot,dm-spl;
> +};
> +
> +&gpio5 {
> +	u-boot,dm-spl;
> +};
> +
> +&uart2 {
> +	u-boot,dm-spl;
> +};
> +
> +&usdhc1 {
> +	u-boot,dm-spl;
> +};
> +
> +&usdhc2 {
> +	u-boot,dm-spl;
> +};
> +
> +&usdhc3 {
> +	u-boot,dm-spl;
> +};

> diff --git a/arch/arm/dts/imx8mn-ddr4-evk.dts
> b/arch/arm/dts/imx8mn-ddr4-evk.dts new file mode 100644
> index 0000000000..9b2c1727a8
> --- /dev/null
> +++ b/arch/arm/dts/imx8mn-ddr4-evk.dts

DTS files shall be added in a separate commit, to avoid one very large
one when you add the board.

> @@ -0,0 +1,221 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2019 NXP
> + */
> +
> +/dts-v1/;
> +
> +#include "imx8mn.dtsi"
> +
> +/ {
> +	model = "NXP i.MX8MNano DDR4 EVK board";
> +	compatible = "fsl,imx8mn-ddr4-evk", "fsl,imx8mn";
> +
> +	chosen {
> +		stdout-path = &uart2;
> +	};
> +
> +	reg_usdhc2_vmmc: regulator-usdhc2 {
> +		compatible = "regulator-fixed";
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
> +		regulator-name = "VSD_3V3";
> +		regulator-min-microvolt = <3300000>;
> +		regulator-max-microvolt = <3300000>;
> +		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
> +		enable-active-high;
> +	};
> +};
> +
> +&iomuxc {
> +	pinctrl-names = "default";
> +
> +	pinctrl_fec1: fec1grp {
> +		fsl,pins = <
> +
> MX8MN_IOMUXC_ENET_MDC_ENET1_MDC		0x3
> +			MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO	0x3
> +			MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3
> 0x1f
> +			MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2
> 0x1f
> +			MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1
> 0x1f
> +			MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0
> 0x1f
> +			MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3
> 0x91
> +			MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2
> 0x91
> +			MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1
> 0x91
> +			MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0
> 0x91
> +			MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC
> 0x1f
> +			MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC
> 0x91
> +
> MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
> +
> MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
> +			MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22	0x19
> +		>;
> +	};
> +
> +	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
> +		fsl,pins = <
> +			MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19
> 0x41
> +		>;
> +	};
> +
> +	pinctrl_uart2: uart2grp {
> +		fsl,pins = <
> +			MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX
> 0x140
> +			MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX
> 0x140
> +		>;
> +	};
> +
> +	pinctrl_usdhc2_gpio: usdhc2grpgpio {
> +		fsl,pins = <
> +			MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15
> 0x1c4
> +		>;
> +	};
> +
> +	pinctrl_usdhc2: usdhc2grp {
> +		fsl,pins = <
> +
> MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK		0x190
> +
> MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d0
> +			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0
> 0x1d0
> +			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1
> 0x1d0
> +			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2
> 0x1d0
> +			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3
> 0x1d0
> +
> MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
> +		>;
> +	};
> +
> +	pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
> +		fsl,pins = <
> +
> MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK		0x194
> +
> MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4
> +			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0
> 0x1d4
> +			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1
> 0x1d4
> +			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2
> 0x1d4
> +			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3
> 0x1d4
> +
> MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
> +		>;
> +	};
> +
> +	pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
> +		fsl,pins = <
> +
> MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK		0x196
> +
> MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d6
> +			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0
> 0x1d6
> +			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1
> 0x1d6
> +			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2
> 0x1d6
> +			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3
> 0x1d6
> +
> MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
> +		>;
> +	};
> +
> +	pinctrl_usdhc3: usdhc3grp {
> +		fsl,pins = <
> +
> MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK		0x40000190
> +
> MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d0
> +
> MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d0
> +
> MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d0
> +
> MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d0
> +
> MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d0
> +
> MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d0
> +
> MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d0
> +
> MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d0
> +
> MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d0
> +
> MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x190
> +		>;
> +	};
> +
> +	pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
> +		fsl,pins = <
> +
> MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK		0x40000194
> +
> MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d4
> +
> MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d4
> +
> MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d4
> +
> MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d4
> +
> MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d4
> +
> MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d4
> +
> MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d4
> +
> MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d4
> +
> MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d4
> +
> MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x194
> +		>;
> +	};
> +
> +	pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
> +		fsl,pins = <
> +
> MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK		0x40000196
> +
> MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d6
> +
> MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d6
> +
> MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d6
> +
> MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d6
> +
> MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d6
> +
> MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d6
> +
> MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d6
> +
> MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d6
> +
> MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d6
> +
> MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x196
> +		>;
> +	};
> +
> +	pinctrl_wdog: wdoggrp {
> +		fsl,pins = <
> +
> MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B		0xc6
> +		>;
> +	};
> +};
> +
> +&fec1 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_fec1>;
> +	phy-mode = "rgmii-id";
> +	phy-handle = <&ethphy0>;
> +	fsl,magic-packet;
> +	status = "okay";
> +
> +	mdio {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		ethphy0: ethernet-phy@0 {
> +			compatible = "ethernet-phy-ieee802.3-c22";
> +			reg = <0>;
> +			at803x,led-act-blind-workaround;
> +			at803x,eee-disabled;
> +			at803x,vddio-1p8v;
> +		};
> +	};
> +};
> +
> +&snvs_pwrkey {
> +	status = "okay";
> +};
> +
> +&uart2 { /* console */
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_uart2>;
> +	status = "okay";
> +};
> +
> +&usdhc2 {
> +	pinctrl-names = "default", "state_100mhz", "state_200mhz";
> +	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
> +	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
> +	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
> +	cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
> +	bus-width = <4>;
> +	vmmc-supply = <&reg_usdhc2_vmmc>;
> +	status = "okay";
> +};
> +
> +&usdhc3 {
> +	pinctrl-names = "default", "state_100mhz", "state_200mhz";
> +	pinctrl-0 = <&pinctrl_usdhc3>;
> +	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
> +	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
> +	bus-width = <8>;
> +	non-removable;
> +	status = "okay";
> +};
> +
> +&wdog1 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_wdog>;
> +	fsl,ext-reset-output;
> +	status = "okay";
> +};
> diff --git a/arch/arm/mach-imx/imx8m/Kconfig
> b/arch/arm/mach-imx/imx8m/Kconfig index b0932f1647..eb4a73b3e2 100644
> --- a/arch/arm/mach-imx/imx8m/Kconfig
> +++ b/arch/arm/mach-imx/imx8m/Kconfig
> @@ -34,9 +34,16 @@ config TARGET_IMX8MM_EVK
>  	select SUPPORT_SPL
>  	select IMX8M_LPDDR4
>  
> +config TARGET_IMX8MN_EVK
> +	bool "imx8mn DDR4 EVK board"
> +	select IMX8MN
> +	select SUPPORT_SPL
> +	select IMX8M_DDR4
> +
>  endchoice
>  
>  source "board/freescale/imx8mq_evk/Kconfig"
>  source "board/freescale/imx8mm_evk/Kconfig"
> +source "board/freescale/imx8mn_evk/Kconfig"
>  
>  endif
> diff --git a/board/freescale/imx8mn_evk/Kconfig
> b/board/freescale/imx8mn_evk/Kconfig new file mode 100644
> index 0000000000..38ac846802
> --- /dev/null
> +++ b/board/freescale/imx8mn_evk/Kconfig
> @@ -0,0 +1,14 @@
> +if TARGET_IMX8MN_EVK
> +
> +config SYS_BOARD
> +	default "imx8mn_evk"
> +
> +config SYS_VENDOR
> +	default "freescale"
> +
> +config SYS_CONFIG_NAME
> +	default "imx8mn_evk"
> +
> +source "board/freescale/common/Kconfig"
> +
> +endif
> diff --git a/board/freescale/imx8mn_evk/MAINTAINERS
> b/board/freescale/imx8mn_evk/MAINTAINERS new file mode 100644
> index 0000000000..3b0653d3c8
> --- /dev/null
> +++ b/board/freescale/imx8mn_evk/MAINTAINERS
> @@ -0,0 +1,6 @@
> +i.MX8MM EVK BOARD
> +M:	Peng Fan <peng.fan@nxp.com>
> +S:	Maintained
> +F:	board/freescale/imx8mn_evk/
> +F:	include/configs/imx8mn_evk.h
> +F:	configs/imx8mn_ddr4_evk_defconfig
> diff --git a/board/freescale/imx8mn_evk/Makefile
> b/board/freescale/imx8mn_evk/Makefile new file mode 100644
> index 0000000000..9511a70c31
> --- /dev/null
> +++ b/board/freescale/imx8mn_evk/Makefile
> @@ -0,0 +1,12 @@
> +#
> +# Copyright 2018 NXP
> +#
> +# SPDX-License-Identifier:      GPL-2.0+
> +#
> +
> +obj-y += imx8mn_evk.o
> +
> +ifdef CONFIG_SPL_BUILD
> +obj-y += spl.o
> +obj-$(CONFIG_IMX8M_DDR4) += ddr4_timing.o
> +endif
> diff --git a/board/freescale/imx8mn_evk/ddr4_timing.c
> b/board/freescale/imx8mn_evk/ddr4_timing.c new file mode 100644
> index 0000000000..d83ea443af
> --- /dev/null
> +++ b/board/freescale/imx8mn_evk/ddr4_timing.c
> @@ -0,0 +1,1213 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2019 NXP
> + *
> + * Generated code from MX8M_DDR_tool
> + * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga
> + */
> +
> +#include <linux/kernel.h>
> +#include <asm/arch/ddr.h>
> +
> +struct dram_cfg_param ddr_ddrc_cfg[] = {
> +	{0x3d400000, 0x81040010},
> +	{0x3d400030, 0x00000020},
> +	{0x3d400034, 0x00221306},
> +	{0x3d400050, 0x00210070},
> +	{0x3d400054, 0x00010008},
> +	{0x3d400060, 0x00000000},
> +	{0x3d400064, 0x0092014a},
> +	{0x3d4000c0, 0x00000000},
> +	{0x3d4000c4, 0x00001000},
> +	{0x3d4000d0, 0xc0030126},
> +	{0x3d4000d4, 0x00770000},
> +	{0x3d4000dc, 0x08340105},
> +	{0x3d4000e0, 0x00180200},
> +	{0x3d4000e4, 0x00110000},
> +	{0x3d4000e8, 0x02000740},
> +	{0x3d4000ec, 0x00000850},
> +	{0x3d4000f4, 0x00000ec7},
> +	{0x3d400100, 0x11122914},
> +	{0x3d400104, 0x0004051c},
> +	{0x3d400108, 0x0608050d},
> +	{0x3d40010c, 0x0000400c},
> +	{0x3d400110, 0x08030409},
> +	{0x3d400114, 0x06060403},
> +	{0x3d40011c, 0x00000606},
> +	{0x3d400120, 0x07070d0c},
> +	{0x3d400124, 0x0002040a},
> +	{0x3d40012c, 0x1809010e},
> +	{0x3d400130, 0x00000008},
> +	{0x3d40013c, 0x00000000},
> +	{0x3d400180, 0x01000040},
> +	{0x3d400184, 0x0000493e},
> +	{0x3d400190, 0x038b8207},
> +	{0x3d400194, 0x02020303},
> +	{0x3d400198, 0x07f04011},
> +	{0x3d40019c, 0x000000b0},
> +	{0x3d4001a0, 0xe0400018},
> +	{0x3d4001a4, 0x0048005a},
> +	{0x3d4001a8, 0x80000000},
> +	{0x3d4001b0, 0x00000001},
> +	{0x3d4001b4, 0x00000b07},
> +	{0x3d4001b8, 0x00000004},
> +	{0x3d4001c0, 0x00000001},
> +	{0x3d4001c4, 0x00000000},
> +	{0x3d400240, 0x06000610},
> +	{0x3d400244, 0x00001323},
> +	{0x3d400200, 0x00003f1f},
> +	{0x3d400204, 0x003f0909},
> +	{0x3d400208, 0x01010100},
> +	{0x3d40020c, 0x01010101},
> +	{0x3d400210, 0x00001f1f},
> +	{0x3d400214, 0x07070707},
> +	{0x3d400218, 0x07070707},
> +	{0x3d40021c, 0x00000f07},
> +	{0x3d400220, 0x00003f01},
> +	{0x3d402050, 0x00210070},
> +	{0x3d402064, 0x00180037},
> +	{0x3d4020dc, 0x00000105},
> +	{0x3d4020e0, 0x00000000},
> +	{0x3d4020e8, 0x02000740},
> +	{0x3d4020ec, 0x00000050},
> +	{0x3d402100, 0x08030604},
> +	{0x3d402104, 0x00020205},
> +	{0x3d402108, 0x05050309},
> +	{0x3d40210c, 0x0000400c},
> +	{0x3d402110, 0x02030202},
> +	{0x3d402114, 0x03030202},
> +	{0x3d402118, 0x0a070008},
> +	{0x3d40211c, 0x00000d09},
> +	{0x3d402120, 0x08084b09},
> +	{0x3d402124, 0x00020308},
> +	{0x3d402128, 0x000f0d06},
> +	{0x3d40212c, 0x12060111},
> +	{0x3d402130, 0x00000008},
> +	{0x3d40213c, 0x00000000},
> +	{0x3d402180, 0x01000040},
> +	{0x3d402190, 0x03848204},
> +	{0x3d402194, 0x02020303},
> +	{0x3d4021b4, 0x00000404},
> +	{0x3d4021b8, 0x00000004},
> +	{0x3d402240, 0x07000600},
> +	{0x3d403050, 0x00210070},
> +	{0x3d403064, 0x0006000d},
> +	{0x3d4030dc, 0x00000105},
> +	{0x3d4030e0, 0x00000000},
> +	{0x3d4030e8, 0x02000740},
> +	{0x3d4030ec, 0x00000050},
> +	{0x3d403100, 0x07010101},
> +	{0x3d403104, 0x00020202},
> +	{0x3d403108, 0x05050309},
> +	{0x3d40310c, 0x0000400c},
> +	{0x3d403110, 0x01030201},
> +	{0x3d403114, 0x03030202},
> +	{0x3d40311c, 0x00000303},
> +	{0x3d403120, 0x02020d02},
> +	{0x3d403124, 0x00020208},
> +	{0x3d403128, 0x000f0d06},
> +	{0x3d40312c, 0x0e02010e},
> +	{0x3d403130, 0x00000008},
> +	{0x3d40313c, 0x00000000},
> +	{0x3d403180, 0x01000040},
> +	{0x3d403190, 0x03848204},
> +	{0x3d403194, 0x02020303},
> +	{0x3d4031b4, 0x00000404},
> +	{0x3d4031b8, 0x00000004},
> +	{0x3d403240, 0x07000600},
> +
> +	/* performance setting */
> +	{ 0x3d400250, 0x00001f05 },
> +	{ 0x3d400254, 0x1f },
> +	{ 0x3d400264, 0x900003ff },
> +	{ 0x3d40026c, 0x200003ff },
> +	{ 0x3d400494, 0x01000e00 },
> +	{ 0x3d400498, 0x03ff0000 },
> +	{ 0x3d40049c, 0x01000e00 },
> +	{ 0x3d4004a0, 0x03ff0000 },
> +};

Isn't there auto training code for i.MX8 as it is for i.MX6Q?

For example: 
https://gitlab.denx.de/u-boot/u-boot/blob/master/arch/arm/mach-imx/mx6/ddr.c
https://gitlab.denx.de/u-boot/u-boot/blob/master/arch/arm/mach-imx/ddrmc-vf610-calibration.c


> +
> +/* PHY Initialize Configuration */
> +struct dram_cfg_param ddr_ddrphy_cfg[] = {
> +	{0x0001005f, 0x000002fd},
> +	{0x0001015f, 0x000002fd},
> +	{0x0001105f, 0x000002fd},
> +	{0x0001115f, 0x000002fd},
> +	{0x0011005f, 0x000002fd},
> +	{0x0011015f, 0x000002fd},
> +	{0x0011105f, 0x000002fd},
> +	{0x0011115f, 0x000002fd},
> +	{0x0021005f, 0x000002fd},
> +	{0x0021015f, 0x000002fd},
> +	{0x0021105f, 0x000002fd},
> +	{0x0021115f, 0x000002fd},
> +	{0x00000055, 0x00000355},
> +	{0x00001055, 0x00000355},
> +	{0x00002055, 0x00000355},
> +	{0x00003055, 0x00000355},
> +	{0x00004055, 0x00000055},
> +	{0x00005055, 0x00000055},
> +	{0x00006055, 0x00000355},
> +	{0x00007055, 0x00000355},
> +	{0x00008055, 0x00000355},
> +	{0x00009055, 0x00000355},
> +	{0x000200c5, 0x0000000a},
> +	{0x001200c5, 0x00000007},
> +	{0x002200c5, 0x00000007},
> +	{0x0002002e, 0x00000002},
> +	{0x0012002e, 0x00000002},
> +	{0x0022002e, 0x00000002},
> +	{0x00020024, 0x00000008},
> +	{0x0002003a, 0x00000002},
> +	{0x0002007d, 0x00000212},
> +	{0x0002007c, 0x00000061},
> +	{0x00120024, 0x00000008},
> +	{0x0002003a, 0x00000002},
> +	{0x0012007d, 0x00000212},
> +	{0x0012007c, 0x00000061},
> +	{0x00220024, 0x00000008},
> +	{0x0002003a, 0x00000002},
> +	{0x0022007d, 0x00000212},
> +	{0x0022007c, 0x00000061},
> +	{0x00020056, 0x00000006},
> +	{0x00120056, 0x0000000a},
> +	{0x00220056, 0x0000000a},
> +	{0x0001004d, 0x0000001a},
> +	{0x0001014d, 0x0000001a},
> +	{0x0001104d, 0x0000001a},
> +	{0x0001114d, 0x0000001a},
> +	{0x0011004d, 0x0000001a},
> +	{0x0011014d, 0x0000001a},
> +	{0x0011104d, 0x0000001a},
> +	{0x0011114d, 0x0000001a},
> +	{0x0021004d, 0x0000001a},
> +	{0x0021014d, 0x0000001a},
> +	{0x0021104d, 0x0000001a},
> +	{0x0021114d, 0x0000001a},
> +	{0x00010049, 0x00000e38},
> +	{0x00010149, 0x00000e38},
> +	{0x00011049, 0x00000e38},
> +	{0x00011149, 0x00000e38},
> +	{0x00110049, 0x00000e38},
> +	{0x00110149, 0x00000e38},
> +	{0x00111049, 0x00000e38},
> +	{0x00111149, 0x00000e38},
> +	{0x00210049, 0x00000e38},
> +	{0x00210149, 0x00000e38},
> +	{0x00211049, 0x00000e38},
> +	{0x00211149, 0x00000e38},
> +	{0x00000043, 0x00000063},
> +	{0x00001043, 0x00000063},
> +	{0x00002043, 0x00000063},
> +	{0x00003043, 0x00000063},
> +	{0x00004043, 0x00000063},
> +	{0x00005043, 0x00000063},
> +	{0x00006043, 0x00000063},
> +	{0x00007043, 0x00000063},
> +	{0x00008043, 0x00000063},
> +	{0x00009043, 0x00000063},
> +	{0x00020018, 0x00000001},
> +	{0x00020075, 0x00000002},
> +	{0x00020050, 0x00000000},
> +	{0x00020008, 0x00000258},
> +	{0x00120008, 0x00000064},
> +	{0x00220008, 0x00000019},
> +	{0x00020088, 0x00000009},
> +	{0x000200b2, 0x00000268},
> +	{0x00010043, 0x000005b1},
> +	{0x00010143, 0x000005b1},
> +	{0x00011043, 0x000005b1},
> +	{0x00011143, 0x000005b1},
> +	{0x001200b2, 0x00000268},
> +	{0x00110043, 0x000005b1},
> +	{0x00110143, 0x000005b1},
> +	{0x00111043, 0x000005b1},
> +	{0x00111143, 0x000005b1},
> +	{0x002200b2, 0x00000268},
> +	{0x00210043, 0x000005b1},
> +	{0x00210143, 0x000005b1},
> +	{0x00211043, 0x000005b1},
> +	{0x00211143, 0x000005b1},
> +	{0x0002005b, 0x00007529},
> +	{0x0002005c, 0x00000000},
> +	{0x000200fa, 0x00000001},
> +	{0x001200fa, 0x00000001},
> +	{0x002200fa, 0x00000001},
> +	{0x00020019, 0x00000005},
> +	{0x00120019, 0x00000005},
> +	{0x00220019, 0x00000005},
> +	{0x000200f0, 0x00005665},
> +	{0x000200f1, 0x00005555},
> +	{0x000200f2, 0x00005555},
> +	{0x000200f3, 0x00005555},
> +	{0x000200f4, 0x00005555},
> +	{0x000200f5, 0x00005555},
> +	{0x000200f6, 0x00005555},
> +	{0x000200f7, 0x0000f000},
> +	{0x0001004a, 0x00000500},
> +	{0x0001104a, 0x00000500},
> +	{0x00020025, 0x00000000},
> +	{0x0002002d, 0x00000000},
> +	{0x0012002d, 0x00000000},
> +	{0x0022002d, 0x00000000},
> +	{0x0002002c, 0x00000000},
> +	{0x000200c7, 0x00000021},
> +	{0x000200ca, 0x00000024},
> +	{0x000200cc, 0x000001f7},
> +	{0x001200c7, 0x00000021},
> +	{0x001200ca, 0x00000024},
> +	{0x001200cc, 0x000001f7},
> +	{0x002200c7, 0x00000021},
> +	{0x002200ca, 0x00000024},
> +	{0x002200cc, 0x000001f7},
> +};
> +
> +/* ddr phy trained csr */
> +struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
> +	{0x0200b2, 0x0},
> +	{0x1200b2, 0x0},
> +	{0x2200b2, 0x0},
> +	{0x0200cb, 0x0},
> +	{0x010043, 0x0},
> +	{0x110043, 0x0},
> +	{0x210043, 0x0},
> +	{0x010143, 0x0},
> +	{0x110143, 0x0},
> +	{0x210143, 0x0},
> +	{0x011043, 0x0},
> +	{0x111043, 0x0},
> +	{0x211043, 0x0},
> +	{0x011143, 0x0},
> +	{0x111143, 0x0},
> +	{0x211143, 0x0},
> +	{0x000080, 0x0},
> +	{0x100080, 0x0},
> +	{0x200080, 0x0},
> +	{0x001080, 0x0},
> +	{0x101080, 0x0},
> +	{0x201080, 0x0},
> +	{0x002080, 0x0},
> +	{0x102080, 0x0},
> +	{0x202080, 0x0},
> +	{0x003080, 0x0},
> +	{0x103080, 0x0},
> +	{0x203080, 0x0},
> +	{0x004080, 0x0},
> +	{0x104080, 0x0},
> +	{0x204080, 0x0},
> +	{0x005080, 0x0},
> +	{0x105080, 0x0},
> +	{0x205080, 0x0},
> +	{0x006080, 0x0},
> +	{0x106080, 0x0},
> +	{0x206080, 0x0},
> +	{0x007080, 0x0},
> +	{0x107080, 0x0},
> +	{0x207080, 0x0},
> +	{0x008080, 0x0},
> +	{0x108080, 0x0},
> +	{0x208080, 0x0},
> +	{0x009080, 0x0},
> +	{0x109080, 0x0},
> +	{0x209080, 0x0},
> +	{0x010080, 0x0},
> +	{0x110080, 0x0},
> +	{0x210080, 0x0},
> +	{0x010180, 0x0},
> +	{0x110180, 0x0},
> +	{0x210180, 0x0},
> +	{0x010081, 0x0},
> +	{0x110081, 0x0},
> +	{0x210081, 0x0},
> +	{0x010181, 0x0},
> +	{0x110181, 0x0},
> +	{0x210181, 0x0},
> +	{0x010082, 0x0},
> +	{0x110082, 0x0},
> +	{0x210082, 0x0},
> +	{0x010182, 0x0},
> +	{0x110182, 0x0},
> +	{0x210182, 0x0},
> +	{0x010083, 0x0},
> +	{0x110083, 0x0},
> +	{0x210083, 0x0},
> +	{0x010183, 0x0},
> +	{0x110183, 0x0},
> +	{0x210183, 0x0},
> +	{0x011080, 0x0},
> +	{0x111080, 0x0},
> +	{0x211080, 0x0},
> +	{0x011180, 0x0},
> +	{0x111180, 0x0},
> +	{0x211180, 0x0},
> +	{0x011081, 0x0},
> +	{0x111081, 0x0},
> +	{0x211081, 0x0},
> +	{0x011181, 0x0},
> +	{0x111181, 0x0},
> +	{0x211181, 0x0},
> +	{0x011082, 0x0},
> +	{0x111082, 0x0},
> +	{0x211082, 0x0},
> +	{0x011182, 0x0},
> +	{0x111182, 0x0},
> +	{0x211182, 0x0},
> +	{0x011083, 0x0},
> +	{0x111083, 0x0},
> +	{0x211083, 0x0},
> +	{0x011183, 0x0},
> +	{0x111183, 0x0},
> +	{0x211183, 0x0},
> +	{0x0100d0, 0x0},
> +	{0x1100d0, 0x0},
> +	{0x2100d0, 0x0},
> +	{0x0101d0, 0x0},
> +	{0x1101d0, 0x0},
> +	{0x2101d0, 0x0},
> +	{0x0100d1, 0x0},
> +	{0x1100d1, 0x0},
> +	{0x2100d1, 0x0},
> +	{0x0101d1, 0x0},
> +	{0x1101d1, 0x0},
> +	{0x2101d1, 0x0},
> +	{0x0100d2, 0x0},
> +	{0x1100d2, 0x0},
> +	{0x2100d2, 0x0},
> +	{0x0101d2, 0x0},
> +	{0x1101d2, 0x0},
> +	{0x2101d2, 0x0},
> +	{0x0100d3, 0x0},
> +	{0x1100d3, 0x0},
> +	{0x2100d3, 0x0},
> +	{0x0101d3, 0x0},
> +	{0x1101d3, 0x0},
> +	{0x2101d3, 0x0},
> +	{0x0110d0, 0x0},
> +	{0x1110d0, 0x0},
> +	{0x2110d0, 0x0},
> +	{0x0111d0, 0x0},
> +	{0x1111d0, 0x0},
> +	{0x2111d0, 0x0},
> +	{0x0110d1, 0x0},
> +	{0x1110d1, 0x0},
> +	{0x2110d1, 0x0},
> +	{0x0111d1, 0x0},
> +	{0x1111d1, 0x0},
> +	{0x2111d1, 0x0},
> +	{0x0110d2, 0x0},
> +	{0x1110d2, 0x0},
> +	{0x2110d2, 0x0},
> +	{0x0111d2, 0x0},
> +	{0x1111d2, 0x0},
> +	{0x2111d2, 0x0},
> +	{0x0110d3, 0x0},
> +	{0x1110d3, 0x0},
> +	{0x2110d3, 0x0},
> +	{0x0111d3, 0x0},
> +	{0x1111d3, 0x0},
> +	{0x2111d3, 0x0},
> +	{0x010068, 0x0},
> +	{0x010168, 0x0},
> +	{0x010268, 0x0},
> +	{0x010368, 0x0},
> +	{0x010468, 0x0},
> +	{0x010568, 0x0},
> +	{0x010668, 0x0},
> +	{0x010768, 0x0},
> +	{0x010868, 0x0},
> +	{0x010069, 0x0},
> +	{0x010169, 0x0},
> +	{0x010269, 0x0},
> +	{0x010369, 0x0},
> +	{0x010469, 0x0},
> +	{0x010569, 0x0},
> +	{0x010669, 0x0},
> +	{0x010769, 0x0},
> +	{0x010869, 0x0},
> +	{0x01006a, 0x0},
> +	{0x01016a, 0x0},
> +	{0x01026a, 0x0},
> +	{0x01036a, 0x0},
> +	{0x01046a, 0x0},
> +	{0x01056a, 0x0},
> +	{0x01066a, 0x0},
> +	{0x01076a, 0x0},
> +	{0x01086a, 0x0},
> +	{0x01006b, 0x0},
> +	{0x01016b, 0x0},
> +	{0x01026b, 0x0},
> +	{0x01036b, 0x0},
> +	{0x01046b, 0x0},
> +	{0x01056b, 0x0},
> +	{0x01066b, 0x0},
> +	{0x01076b, 0x0},
> +	{0x01086b, 0x0},
> +	{0x011068, 0x0},
> +	{0x011168, 0x0},
> +	{0x011268, 0x0},
> +	{0x011368, 0x0},
> +	{0x011468, 0x0},
> +	{0x011568, 0x0},
> +	{0x011668, 0x0},
> +	{0x011768, 0x0},
> +	{0x011868, 0x0},
> +	{0x011069, 0x0},
> +	{0x011169, 0x0},
> +	{0x011269, 0x0},
> +	{0x011369, 0x0},
> +	{0x011469, 0x0},
> +	{0x011569, 0x0},
> +	{0x011669, 0x0},
> +	{0x011769, 0x0},
> +	{0x011869, 0x0},
> +	{0x01106a, 0x0},
> +	{0x01116a, 0x0},
> +	{0x01126a, 0x0},
> +	{0x01136a, 0x0},
> +	{0x01146a, 0x0},
> +	{0x01156a, 0x0},
> +	{0x01166a, 0x0},
> +	{0x01176a, 0x0},
> +	{0x01186a, 0x0},
> +	{0x01106b, 0x0},
> +	{0x01116b, 0x0},
> +	{0x01126b, 0x0},
> +	{0x01136b, 0x0},
> +	{0x01146b, 0x0},
> +	{0x01156b, 0x0},
> +	{0x01166b, 0x0},
> +	{0x01176b, 0x0},
> +	{0x01186b, 0x0},
> +	{0x01008c, 0x0},
> +	{0x11008c, 0x0},
> +	{0x21008c, 0x0},
> +	{0x01018c, 0x0},
> +	{0x11018c, 0x0},
> +	{0x21018c, 0x0},
> +	{0x01008d, 0x0},
> +	{0x11008d, 0x0},
> +	{0x21008d, 0x0},
> +	{0x01018d, 0x0},
> +	{0x11018d, 0x0},
> +	{0x21018d, 0x0},
> +	{0x01008e, 0x0},
> +	{0x11008e, 0x0},
> +	{0x21008e, 0x0},
> +	{0x01018e, 0x0},
> +	{0x11018e, 0x0},
> +	{0x21018e, 0x0},
> +	{0x01008f, 0x0},
> +	{0x11008f, 0x0},
> +	{0x21008f, 0x0},
> +	{0x01018f, 0x0},
> +	{0x11018f, 0x0},
> +	{0x21018f, 0x0},
> +	{0x01108c, 0x0},
> +	{0x11108c, 0x0},
> +	{0x21108c, 0x0},
> +	{0x01118c, 0x0},
> +	{0x11118c, 0x0},
> +	{0x21118c, 0x0},
> +	{0x01108d, 0x0},
> +	{0x11108d, 0x0},
> +	{0x21108d, 0x0},
> +	{0x01118d, 0x0},
> +	{0x11118d, 0x0},
> +	{0x21118d, 0x0},
> +	{0x01108e, 0x0},
> +	{0x11108e, 0x0},
> +	{0x21108e, 0x0},
> +	{0x01118e, 0x0},
> +	{0x11118e, 0x0},
> +	{0x21118e, 0x0},
> +	{0x01108f, 0x0},
> +	{0x11108f, 0x0},
> +	{0x21108f, 0x0},
> +	{0x01118f, 0x0},
> +	{0x11118f, 0x0},
> +	{0x21118f, 0x0},
> +	{0x0100c0, 0x0},
> +	{0x1100c0, 0x0},
> +	{0x2100c0, 0x0},
> +	{0x0101c0, 0x0},
> +	{0x1101c0, 0x0},
> +	{0x2101c0, 0x0},
> +	{0x0102c0, 0x0},
> +	{0x1102c0, 0x0},
> +	{0x2102c0, 0x0},
> +	{0x0103c0, 0x0},
> +	{0x1103c0, 0x0},
> +	{0x2103c0, 0x0},
> +	{0x0104c0, 0x0},
> +	{0x1104c0, 0x0},
> +	{0x2104c0, 0x0},
> +	{0x0105c0, 0x0},
> +	{0x1105c0, 0x0},
> +	{0x2105c0, 0x0},
> +	{0x0106c0, 0x0},
> +	{0x1106c0, 0x0},
> +	{0x2106c0, 0x0},
> +	{0x0107c0, 0x0},
> +	{0x1107c0, 0x0},
> +	{0x2107c0, 0x0},
> +	{0x0108c0, 0x0},
> +	{0x1108c0, 0x0},
> +	{0x2108c0, 0x0},
> +	{0x0100c1, 0x0},
> +	{0x1100c1, 0x0},
> +	{0x2100c1, 0x0},
> +	{0x0101c1, 0x0},
> +	{0x1101c1, 0x0},
> +	{0x2101c1, 0x0},
> +	{0x0102c1, 0x0},
> +	{0x1102c1, 0x0},
> +	{0x2102c1, 0x0},
> +	{0x0103c1, 0x0},
> +	{0x1103c1, 0x0},
> +	{0x2103c1, 0x0},
> +	{0x0104c1, 0x0},
> +	{0x1104c1, 0x0},
> +	{0x2104c1, 0x0},
> +	{0x0105c1, 0x0},
> +	{0x1105c1, 0x0},
> +	{0x2105c1, 0x0},
> +	{0x0106c1, 0x0},
> +	{0x1106c1, 0x0},
> +	{0x2106c1, 0x0},
> +	{0x0107c1, 0x0},
> +	{0x1107c1, 0x0},
> +	{0x2107c1, 0x0},
> +	{0x0108c1, 0x0},
> +	{0x1108c1, 0x0},
> +	{0x2108c1, 0x0},
> +	{0x0100c2, 0x0},
> +	{0x1100c2, 0x0},
> +	{0x2100c2, 0x0},
> +	{0x0101c2, 0x0},
> +	{0x1101c2, 0x0},
> +	{0x2101c2, 0x0},
> +	{0x0102c2, 0x0},
> +	{0x1102c2, 0x0},
> +	{0x2102c2, 0x0},
> +	{0x0103c2, 0x0},
> +	{0x1103c2, 0x0},
> +	{0x2103c2, 0x0},
> +	{0x0104c2, 0x0},
> +	{0x1104c2, 0x0},
> +	{0x2104c2, 0x0},
> +	{0x0105c2, 0x0},
> +	{0x1105c2, 0x0},
> +	{0x2105c2, 0x0},
> +	{0x0106c2, 0x0},
> +	{0x1106c2, 0x0},
> +	{0x2106c2, 0x0},
> +	{0x0107c2, 0x0},
> +	{0x1107c2, 0x0},
> +	{0x2107c2, 0x0},
> +	{0x0108c2, 0x0},
> +	{0x1108c2, 0x0},
> +	{0x2108c2, 0x0},
> +	{0x0100c3, 0x0},
> +	{0x1100c3, 0x0},
> +	{0x2100c3, 0x0},
> +	{0x0101c3, 0x0},
> +	{0x1101c3, 0x0},
> +	{0x2101c3, 0x0},
> +	{0x0102c3, 0x0},
> +	{0x1102c3, 0x0},
> +	{0x2102c3, 0x0},
> +	{0x0103c3, 0x0},
> +	{0x1103c3, 0x0},
> +	{0x2103c3, 0x0},
> +	{0x0104c3, 0x0},
> +	{0x1104c3, 0x0},
> +	{0x2104c3, 0x0},
> +	{0x0105c3, 0x0},
> +	{0x1105c3, 0x0},
> +	{0x2105c3, 0x0},
> +	{0x0106c3, 0x0},
> +	{0x1106c3, 0x0},
> +	{0x2106c3, 0x0},
> +	{0x0107c3, 0x0},
> +	{0x1107c3, 0x0},
> +	{0x2107c3, 0x0},
> +	{0x0108c3, 0x0},
> +	{0x1108c3, 0x0},
> +	{0x2108c3, 0x0},
> +	{0x0110c0, 0x0},
> +	{0x1110c0, 0x0},
> +	{0x2110c0, 0x0},
> +	{0x0111c0, 0x0},
> +	{0x1111c0, 0x0},
> +	{0x2111c0, 0x0},
> +	{0x0112c0, 0x0},
> +	{0x1112c0, 0x0},
> +	{0x2112c0, 0x0},
> +	{0x0113c0, 0x0},
> +	{0x1113c0, 0x0},
> +	{0x2113c0, 0x0},
> +	{0x0114c0, 0x0},
> +	{0x1114c0, 0x0},
> +	{0x2114c0, 0x0},
> +	{0x0115c0, 0x0},
> +	{0x1115c0, 0x0},
> +	{0x2115c0, 0x0},
> +	{0x0116c0, 0x0},
> +	{0x1116c0, 0x0},
> +	{0x2116c0, 0x0},
> +	{0x0117c0, 0x0},
> +	{0x1117c0, 0x0},
> +	{0x2117c0, 0x0},
> +	{0x0118c0, 0x0},
> +	{0x1118c0, 0x0},
> +	{0x2118c0, 0x0},
> +	{0x0110c1, 0x0},
> +	{0x1110c1, 0x0},
> +	{0x2110c1, 0x0},
> +	{0x0111c1, 0x0},
> +	{0x1111c1, 0x0},
> +	{0x2111c1, 0x0},
> +	{0x0112c1, 0x0},
> +	{0x1112c1, 0x0},
> +	{0x2112c1, 0x0},
> +	{0x0113c1, 0x0},
> +	{0x1113c1, 0x0},
> +	{0x2113c1, 0x0},
> +	{0x0114c1, 0x0},
> +	{0x1114c1, 0x0},
> +	{0x2114c1, 0x0},
> +	{0x0115c1, 0x0},
> +	{0x1115c1, 0x0},
> +	{0x2115c1, 0x0},
> +	{0x0116c1, 0x0},
> +	{0x1116c1, 0x0},
> +	{0x2116c1, 0x0},
> +	{0x0117c1, 0x0},
> +	{0x1117c1, 0x0},
> +	{0x2117c1, 0x0},
> +	{0x0118c1, 0x0},
> +	{0x1118c1, 0x0},
> +	{0x2118c1, 0x0},
> +	{0x0110c2, 0x0},
> +	{0x1110c2, 0x0},
> +	{0x2110c2, 0x0},
> +	{0x0111c2, 0x0},
> +	{0x1111c2, 0x0},
> +	{0x2111c2, 0x0},
> +	{0x0112c2, 0x0},
> +	{0x1112c2, 0x0},
> +	{0x2112c2, 0x0},
> +	{0x0113c2, 0x0},
> +	{0x1113c2, 0x0},
> +	{0x2113c2, 0x0},
> +	{0x0114c2, 0x0},
> +	{0x1114c2, 0x0},
> +	{0x2114c2, 0x0},
> +	{0x0115c2, 0x0},
> +	{0x1115c2, 0x0},
> +	{0x2115c2, 0x0},
> +	{0x0116c2, 0x0},
> +	{0x1116c2, 0x0},
> +	{0x2116c2, 0x0},
> +	{0x0117c2, 0x0},
> +	{0x1117c2, 0x0},
> +	{0x2117c2, 0x0},
> +	{0x0118c2, 0x0},
> +	{0x1118c2, 0x0},
> +	{0x2118c2, 0x0},
> +	{0x0110c3, 0x0},
> +	{0x1110c3, 0x0},
> +	{0x2110c3, 0x0},
> +	{0x0111c3, 0x0},
> +	{0x1111c3, 0x0},
> +	{0x2111c3, 0x0},
> +	{0x0112c3, 0x0},
> +	{0x1112c3, 0x0},
> +	{0x2112c3, 0x0},
> +	{0x0113c3, 0x0},
> +	{0x1113c3, 0x0},
> +	{0x2113c3, 0x0},
> +	{0x0114c3, 0x0},
> +	{0x1114c3, 0x0},
> +	{0x2114c3, 0x0},
> +	{0x0115c3, 0x0},
> +	{0x1115c3, 0x0},
> +	{0x2115c3, 0x0},
> +	{0x0116c3, 0x0},
> +	{0x1116c3, 0x0},
> +	{0x2116c3, 0x0},
> +	{0x0117c3, 0x0},
> +	{0x1117c3, 0x0},
> +	{0x2117c3, 0x0},
> +	{0x0118c3, 0x0},
> +	{0x1118c3, 0x0},
> +	{0x2118c3, 0x0},
> +	{0x010020, 0x0},
> +	{0x110020, 0x0},
> +	{0x210020, 0x0},
> +	{0x011020, 0x0},
> +	{0x111020, 0x0},
> +	{0x211020, 0x0},
> +	{0x02007d, 0x0},
> +	{0x12007d, 0x0},
> +	{0x22007d, 0x0},
> +	{0x010040, 0x0},
> +	{0x010140, 0x0},
> +	{0x010240, 0x0},
> +	{0x010340, 0x0},
> +	{0x010440, 0x0},
> +	{0x010540, 0x0},
> +	{0x010640, 0x0},
> +	{0x010740, 0x0},
> +	{0x010840, 0x0},
> +	{0x010030, 0x0},
> +	{0x010130, 0x0},
> +	{0x010230, 0x0},
> +	{0x010330, 0x0},
> +	{0x010430, 0x0},
> +	{0x010530, 0x0},
> +	{0x010630, 0x0},
> +	{0x010730, 0x0},
> +	{0x010830, 0x0},
> +	{0x011040, 0x0},
> +	{0x011140, 0x0},
> +	{0x011240, 0x0},
> +	{0x011340, 0x0},
> +	{0x011440, 0x0},
> +	{0x011540, 0x0},
> +	{0x011640, 0x0},
> +	{0x011740, 0x0},
> +	{0x011840, 0x0},
> +	{0x011030, 0x0},
> +	{0x011130, 0x0},
> +	{0x011230, 0x0},
> +	{0x011330, 0x0},
> +	{0x011430, 0x0},
> +	{0x011530, 0x0},
> +	{0x011630, 0x0},
> +	{0x011730, 0x0},
> +	{0x011830, 0x0},
> +};
> +
> +/* P0 message block paremeter for training firmware */
> +struct dram_cfg_param ddr_fsp0_cfg[] = {
> +	{0x000d0000, 0x00000000},
> +	{0x00020060, 0x00000002},
> +	{0x00054000, 0x00000000},
> +	{0x00054001, 0x00000000},
> +	{0x00054002, 0x00000000},
> +	{0x00054003, 0x00000960},
> +	{0x00054004, 0x00000002},
> +	{0x00054005, 0x00000000},
> +	{0x00054006, 0x0000025e},
> +	{0x00054007, 0x00001000},
> +	{0x00054008, 0x00000101},
> +	{0x00054009, 0x00000000},
> +	{0x0005400a, 0x00000000},
> +	{0x0005400b, 0x0000031f},
> +	{0x0005400c, 0x000000c8},
> +	{0x0005400d, 0x00000100},
> +	{0x0005400e, 0x00000000},
> +	{0x0005400f, 0x00000000},
> +	{0x00054010, 0x00000000},
> +	{0x00054011, 0x00000000},
> +	{0x00054012, 0x00000001},
> +	{0x0005402f, 0x00000834},
> +	{0x00054030, 0x00000105},
> +	{0x00054031, 0x00000018},
> +	{0x00054032, 0x00000200},
> +	{0x00054033, 0x00000200},
> +	{0x00054034, 0x00000740},
> +	{0x00054035, 0x00000850},
> +	{0x00054036, 0x00000103},
> +	{0x00054037, 0x00000000},
> +	{0x00054038, 0x00000000},
> +	{0x00054039, 0x00000000},
> +	{0x0005403a, 0x00000000},
> +	{0x0005403b, 0x00000000},
> +	{0x0005403c, 0x00000000},
> +	{0x0005403d, 0x00000000},
> +	{0x0005403e, 0x00000000},
> +	{0x0005403f, 0x00001221},
> +	{0x000541fc, 0x00000100},
> +	{0x000d0000, 0x00000001},
> +};
> +
> +/* P1 message block paremeter for training firmware */
> +struct dram_cfg_param ddr_fsp1_cfg[] = {
> +	{0x000d0000, 0x00000000},
> +	{0x00054000, 0x00000000},
> +	{0x00054001, 0x00000000},
> +	{0x00054002, 0x00000101},
> +	{0x00054003, 0x00000190},
> +	{0x00054004, 0x00000002},
> +	{0x00054005, 0x00000000},
> +	{0x00054006, 0x0000025e},
> +	{0x00054007, 0x00001000},
> +	{0x00054008, 0x00000101},
> +	{0x00054009, 0x00000000},
> +	{0x0005400a, 0x00000000},
> +	{0x0005400b, 0x0000021f},
> +	{0x0005400c, 0x000000c8},
> +	{0x0005400d, 0x00000100},
> +	{0x0005400e, 0x00000000},
> +	{0x0005400f, 0x00000000},
> +	{0x00054010, 0x00000000},
> +	{0x00054011, 0x00000000},
> +	{0x00054012, 0x00000001},
> +	{0x0005402f, 0x00000000},
> +	{0x00054030, 0x00000105},
> +	{0x00054031, 0x00000000},
> +	{0x00054032, 0x00000000},
> +	{0x00054033, 0x00000200},
> +	{0x00054034, 0x00000740},
> +	{0x00054035, 0x00000050},
> +	{0x00054036, 0x00000103},
> +	{0x00054037, 0x00000000},
> +	{0x00054038, 0x00000000},
> +	{0x00054039, 0x00000000},
> +	{0x0005403a, 0x00000000},
> +	{0x0005403b, 0x00000000},
> +	{0x0005403c, 0x00000000},
> +	{0x0005403d, 0x00000000},
> +	{0x0005403e, 0x00000000},
> +	{0x0005403f, 0x00001221},
> +	{0x000541fc, 0x00000100},
> +	{0x000d0000, 0x00000001},
> +};
> +
> +/* P2 message block paremeter for training firmware */
> +struct dram_cfg_param ddr_fsp2_cfg[] = {
> +	{0x000d0000, 0x00000000},
> +	{0x00054000, 0x00000000},
> +	{0x00054001, 0x00000000},
> +	{0x00054002, 0x00000102},
> +	{0x00054003, 0x00000064},
> +	{0x00054004, 0x00000002},
> +	{0x00054005, 0x00000000},
> +	{0x00054006, 0x0000025e},
> +	{0x00054007, 0x00001000},
> +	{0x00054008, 0x00000101},
> +	{0x00054009, 0x00000000},
> +	{0x0005400a, 0x00000000},
> +	{0x0005400b, 0x0000021f},
> +	{0x0005400c, 0x000000c8},
> +	{0x0005400d, 0x00000100},
> +	{0x0005400e, 0x00000000},
> +	{0x0005400f, 0x00000000},
> +	{0x00054010, 0x00000000},
> +	{0x00054011, 0x00000000},
> +	{0x00054012, 0x00000001},
> +	{0x0005402f, 0x00000000},
> +	{0x00054030, 0x00000105},
> +	{0x00054031, 0x00000000},
> +	{0x00054032, 0x00000000},
> +	{0x00054033, 0x00000200},
> +	{0x00054034, 0x00000740},
> +	{0x00054035, 0x00000050},
> +	{0x00054036, 0x00000103},
> +	{0x00054037, 0x00000000},
> +	{0x00054038, 0x00000000},
> +	{0x00054039, 0x00000000},
> +	{0x0005403a, 0x00000000},
> +	{0x0005403b, 0x00000000},
> +	{0x0005403c, 0x00000000},
> +	{0x0005403d, 0x00000000},
> +	{0x0005403e, 0x00000000},
> +	{0x0005403f, 0x00001221},
> +	{0x000541fc, 0x00000100},
> +	{0x000d0000, 0x00000001},
> +};
> +
> +/* P0 2D message block paremeter for training firmware */
> +struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
> +	{0x000d0000, 0x00000000},
> +	{0x00054000, 0x00000000},
> +	{0x00054001, 0x00000000},
> +	{0x00054002, 0x00000000},
> +	{0x00054003, 0x00000960},
> +	{0x00054004, 0x00000002},
> +	{0x00054005, 0x00000000},
> +	{0x00054006, 0x0000025e},
> +	{0x00054007, 0x00001000},
> +	{0x00054008, 0x00000101},
> +	{0x00054009, 0x00000000},
> +	{0x0005400a, 0x00000000},
> +	{0x0005400b, 0x00000061},
> +	{0x0005400c, 0x000000c8},
> +	{0x0005400d, 0x00000100},
> +	{0x0005400e, 0x00001f7f},
> +	{0x0005400f, 0x00000000},
> +	{0x00054010, 0x00000000},
> +	{0x00054011, 0x00000000},
> +	{0x00054012, 0x00000001},
> +	{0x0005402f, 0x00000834},
> +	{0x00054030, 0x00000105},
> +	{0x00054031, 0x00000018},
> +	{0x00054032, 0x00000200},
> +	{0x00054033, 0x00000200},
> +	{0x00054034, 0x00000740},
> +	{0x00054035, 0x00000850},
> +	{0x00054036, 0x00000103},
> +	{0x00054037, 0x00000000},
> +	{0x00054038, 0x00000000},
> +	{0x00054039, 0x00000000},
> +	{0x0005403a, 0x00000000},
> +	{0x0005403b, 0x00000000},
> +	{0x0005403c, 0x00000000},
> +	{0x0005403d, 0x00000000},
> +	{0x0005403e, 0x00000000},
> +	{0x0005403f, 0x00001221},
> +	{0x000541fc, 0x00000100},
> +	{0x000d0000, 0x00000001},
> +};
> +
> +/* DRAM PHY init engine image */
> +struct dram_cfg_param ddr_phy_pie[] = {
> +	{0xd0000, 0x0},
> +	{0x90000, 0x10},
> +	{0x90001, 0x400},
> +	{0x90002, 0x10e},
> +	{0x90003, 0x0},
> +	{0x90004, 0x0},
> +	{0x90005, 0x8},
> +	{0x90029, 0xb},
> +	{0x9002a, 0x480},
> +	{0x9002b, 0x109},
> +	{0x9002c, 0x8},
> +	{0x9002d, 0x448},
> +	{0x9002e, 0x139},
> +	{0x9002f, 0x8},
> +	{0x90030, 0x478},
> +	{0x90031, 0x109},
> +	{0x90032, 0x2},
> +	{0x90033, 0x10},
> +	{0x90034, 0x139},
> +	{0x90035, 0xb},
> +	{0x90036, 0x7c0},
> +	{0x90037, 0x139},
> +	{0x90038, 0x44},
> +	{0x90039, 0x633},
> +	{0x9003a, 0x159},
> +	{0x9003b, 0x14f},
> +	{0x9003c, 0x630},
> +	{0x9003d, 0x159},
> +	{0x9003e, 0x47},
> +	{0x9003f, 0x633},
> +	{0x90040, 0x149},
> +	{0x90041, 0x4f},
> +	{0x90042, 0x633},
> +	{0x90043, 0x179},
> +	{0x90044, 0x8},
> +	{0x90045, 0xe0},
> +	{0x90046, 0x109},
> +	{0x90047, 0x0},
> +	{0x90048, 0x7c8},
> +	{0x90049, 0x109},
> +	{0x9004a, 0x0},
> +	{0x9004b, 0x1},
> +	{0x9004c, 0x8},
> +	{0x9004d, 0x0},
> +	{0x9004e, 0x45a},
> +	{0x9004f, 0x9},
> +	{0x90050, 0x0},
> +	{0x90051, 0x448},
> +	{0x90052, 0x109},
> +	{0x90053, 0x40},
> +	{0x90054, 0x633},
> +	{0x90055, 0x179},
> +	{0x90056, 0x1},
> +	{0x90057, 0x618},
> +	{0x90058, 0x109},
> +	{0x90059, 0x40c0},
> +	{0x9005a, 0x633},
> +	{0x9005b, 0x149},
> +	{0x9005c, 0x8},
> +	{0x9005d, 0x4},
> +	{0x9005e, 0x48},
> +	{0x9005f, 0x4040},
> +	{0x90060, 0x633},
> +	{0x90061, 0x149},
> +	{0x90062, 0x0},
> +	{0x90063, 0x4},
> +	{0x90064, 0x48},
> +	{0x90065, 0x40},
> +	{0x90066, 0x633},
> +	{0x90067, 0x149},
> +	{0x90068, 0x10},
> +	{0x90069, 0x4},
> +	{0x9006a, 0x18},
> +	{0x9006b, 0x0},
> +	{0x9006c, 0x4},
> +	{0x9006d, 0x78},
> +	{0x9006e, 0x549},
> +	{0x9006f, 0x633},
> +	{0x90070, 0x159},
> +	{0x90071, 0xd49},
> +	{0x90072, 0x633},
> +	{0x90073, 0x159},
> +	{0x90074, 0x94a},
> +	{0x90075, 0x633},
> +	{0x90076, 0x159},
> +	{0x90077, 0x441},
> +	{0x90078, 0x633},
> +	{0x90079, 0x149},
> +	{0x9007a, 0x42},
> +	{0x9007b, 0x633},
> +	{0x9007c, 0x149},
> +	{0x9007d, 0x1},
> +	{0x9007e, 0x633},
> +	{0x9007f, 0x149},
> +	{0x90080, 0x0},
> +	{0x90081, 0xe0},
> +	{0x90082, 0x109},
> +	{0x90083, 0xa},
> +	{0x90084, 0x10},
> +	{0x90085, 0x109},
> +	{0x90086, 0x9},
> +	{0x90087, 0x3c0},
> +	{0x90088, 0x149},
> +	{0x90089, 0x9},
> +	{0x9008a, 0x3c0},
> +	{0x9008b, 0x159},
> +	{0x9008c, 0x18},
> +	{0x9008d, 0x10},
> +	{0x9008e, 0x109},
> +	{0x9008f, 0x0},
> +	{0x90090, 0x3c0},
> +	{0x90091, 0x109},
> +	{0x90092, 0x18},
> +	{0x90093, 0x4},
> +	{0x90094, 0x48},
> +	{0x90095, 0x18},
> +	{0x90096, 0x4},
> +	{0x90097, 0x58},
> +	{0x90098, 0xb},
> +	{0x90099, 0x10},
> +	{0x9009a, 0x109},
> +	{0x9009b, 0x1},
> +	{0x9009c, 0x10},
> +	{0x9009d, 0x109},
> +	{0x9009e, 0x5},
> +	{0x9009f, 0x7c0},
> +	{0x900a0, 0x109},
> +	{0x900a1, 0x0},
> +	{0x900a2, 0x8140},
> +	{0x900a3, 0x10c},
> +	{0x900a4, 0x10},
> +	{0x900a5, 0x8138},
> +	{0x900a6, 0x10c},
> +	{0x900a7, 0x8},
> +	{0x900a8, 0x7c8},
> +	{0x900a9, 0x101},
> +	{0x900aa, 0x8},
> +	{0x900ab, 0x448},
> +	{0x900ac, 0x109},
> +	{0x900ad, 0xf},
> +	{0x900ae, 0x7c0},
> +	{0x900af, 0x109},
> +	{0x900b0, 0x47},
> +	{0x900b1, 0x630},
> +	{0x900b2, 0x109},
> +	{0x900b3, 0x8},
> +	{0x900b4, 0x618},
> +	{0x900b5, 0x109},
> +	{0x900b6, 0x8},
> +	{0x900b7, 0xe0},
> +	{0x900b8, 0x109},
> +	{0x900b9, 0x0},
> +	{0x900ba, 0x7c8},
> +	{0x900bb, 0x109},
> +	{0x900bc, 0x8},
> +	{0x900bd, 0x8140},
> +	{0x900be, 0x10c},
> +	{0x900bf, 0x0},
> +	{0x900c0, 0x1},
> +	{0x900c1, 0x8},
> +	{0x900c2, 0x8},
> +	{0x900c3, 0x4},
> +	{0x900c4, 0x8},
> +	{0x900c5, 0x8},
> +	{0x900c6, 0x7c8},
> +	{0x900c7, 0x101},
> +	{0x90006, 0x0},
> +	{0x90007, 0x0},
> +	{0x90008, 0x8},
> +	{0x90009, 0x0},
> +	{0x9000a, 0x0},
> +	{0x9000b, 0x0},
> +	{0xd00e7, 0x400},
> +	{0x90017, 0x0},
> +	{0x90026, 0x2b},
> +	{0x2000b, 0x4b},
> +	{0x2000c, 0x96},
> +	{0x2000d, 0x5dc},
> +	{0x2000e, 0x2c},
> +	{0x12000b, 0xc},
> +	{0x12000c, 0x16},
> +	{0x12000d, 0xfa},
> +	{0x12000e, 0x10},
> +	{0x22000b, 0x3},
> +	{0x22000c, 0x3},
> +	{0x22000d, 0x3e},
> +	{0x22000e, 0x10},
> +	{0x9000c, 0x0},
> +	{0x9000d, 0x173},
> +	{0x9000e, 0x60},
> +	{0x9000f, 0x6110},
> +	{0x90010, 0x2152},
> +	{0x90011, 0xdfbd},
> +	{0x90012, 0xffff},
> +	{0x90013, 0x6152},
> +	{0x20089, 0x1},
> +	{0x20088, 0x19},
> +	{0xc0080, 0x0},
> +	{0xd0000, 0x1},
> +};
> +

The list of binary data is quite impressive for i.MX8

> +struct dram_fsp_msg ddr_dram_fsp_msg[] = {
> +	{
> +		/* P0 2400mts 1D */
> +		.drate = 2400,
> +		.fw_type = FW_1D_IMAGE,
> +		.fsp_cfg = ddr_fsp0_cfg,
> +		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
> +	},
> +	{
> +		/* P1 400mts 1D */
> +		.drate = 400,
> +		.fw_type = FW_1D_IMAGE,
> +		.fsp_cfg = ddr_fsp1_cfg,
> +		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
> +	},
> +	{
> +		/* P2 100mts 1D */
> +		.drate = 100,
> +		.fw_type = FW_1D_IMAGE,
> +		.fsp_cfg = ddr_fsp2_cfg,
> +		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
> +	},
> +	{
> +		/* P0 2400mts 2D */
> +		.drate = 2400,
> +		.fw_type = FW_2D_IMAGE,
> +		.fsp_cfg = ddr_fsp0_2d_cfg,
> +		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
> +	},
> +};
> +
> +/* ddr timing config params */
> +struct dram_timing_info dram_timing = {
> +	.ddrc_cfg = ddr_ddrc_cfg,
> +	.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
> +	.ddrphy_cfg = ddr_ddrphy_cfg,
> +	.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
> +	.fsp_msg = ddr_dram_fsp_msg,
> +	.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
> +	.ddrphy_trained_csr = ddr_ddrphy_trained_csr,
> +	.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
> +	.ddrphy_pie = ddr_phy_pie,
> +	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
> +	.fsp_table = { 2400, 400, 100,},
> +};
> +
> diff --git a/board/freescale/imx8mn_evk/imx8mn_evk.c
> b/board/freescale/imx8mn_evk/imx8mn_evk.c new file mode 100644
> index 0000000000..badfde911b
> --- /dev/null
> +++ b/board/freescale/imx8mn_evk/imx8mn_evk.c
> @@ -0,0 +1,85 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2019 NXP
> + */
> +
> +#include <common.h>
> +#include <errno.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/imx8mn_pins.h>
> +#include <asm/arch/sys_proto.h>
> +#include <asm/mach-imx/iomux-v3.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define UART_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_FSEL1)
> +#define WDOG_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_ODE |
> PAD_CTL_PUE | PAD_CTL_PE) +
> +static iomux_v3_cfg_t const uart_pads[] = {
> +	IMX8MN_PAD_UART2_RXD__UART2_DCE_RX |
> MUX_PAD_CTRL(UART_PAD_CTRL),
> +	IMX8MN_PAD_UART2_TXD__UART2_DCE_TX |
> MUX_PAD_CTRL(UART_PAD_CTRL), +};
> +
> +static iomux_v3_cfg_t const wdog_pads[] = {
> +	IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B  |
> MUX_PAD_CTRL(WDOG_PAD_CTRL), +};
> +
> +int board_early_init_f(void)
> +{
> +	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
> +
> +	imx_iomux_v3_setup_multiple_pads(wdog_pads,

Shouldn't those pins be configured via DTS/DM? As fair as I see this is
the imx8mn_evk.c file (which seems not to be the SPL).

> ARRAY_SIZE(wdog_pads)); +
> +	set_wdog_reset(wdog);
> +
> +	imx_iomux_v3_setup_multiple_pads(uart_pads,
> ARRAY_SIZE(uart_pads)); +
> +	init_uart_clk(1);

This also seems like not DM/DTS code.

> +
> +	return 0;
> +}
> +
> +#ifdef CONFIG_BOARD_POSTCLK_INIT
> +int board_postclk_init(void)
> +{
> +	/* TODO */
> +	return 0;
> +}
> +#endif
> +
> +int dram_init(void)
> +{
> +	/* rom_pointer[1] contains the size of TEE occupies */
> +	if (rom_pointer[1])
> +		gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1];
> +	else
> +		gd->ram_size = PHYS_SDRAM_SIZE;
> +
> +	return 0;
> +}
> +
> +#ifdef CONFIG_OF_BOARD_SETUP
> +int ft_board_setup(void *blob, bd_t *bd)
> +{
> +	return 0;
> +}
> +#endif
> +
> +int board_init(void)
> +{
> +	return 0;
> +}
> +
> +int board_mmc_get_env_dev(int devno)
> +{
> +	return devno - 1;
> +}

Shouldn't the number of mmc device be get via alias defined in DTS (or
assigned automatically)? 

What is the purpose of this function?

> +
> +int board_late_init(void)
> +{
> +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
> +	env_set("board_name", "DDR4 EVK");
> +	env_set("board_rev", "iMX8MN");
> +#endif
> +	return 0;
> +}
> diff --git a/board/freescale/imx8mn_evk/spl.c
> b/board/freescale/imx8mn_evk/spl.c new file mode 100644
> index 0000000000..aa5f37fde0
> --- /dev/null
> +++ b/board/freescale/imx8mn_evk/spl.c
> @@ -0,0 +1,90 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2019 NXP
> + */
> +
> +#include <common.h>
> +#include <spl.h>
> +#include <asm/io.h>
> +#include <errno.h>
> +#include <asm/arch/imx8mn_pins.h>
> +#include <asm/arch/sys_proto.h>
> +#include <asm/arch/clock.h>
> +#include <asm/gpio.h>
> +#include <asm/arch/ddr.h>
> +#include <asm/mach-imx/boot_mode.h>
> +#include <asm/mach-imx/gpio.h>
> +#include <asm/mach-imx/iomux-v3.h>
> +#include <asm/mach-imx/mxc_i2c.h>
> +
> +#include <dm/uclass.h>
> +#include <dm/device.h>
> +#include <dm/uclass-internal.h>
> +#include <dm/device-internal.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +int spl_board_boot_device(enum boot_device boot_dev_spl)
> +{
> +	return BOOT_DEVICE_BOOTROM;
> +}
> +
> +void spl_dram_init(void)
> +{
> +	ddr_init(&dram_timing);
> +}
> +
> +void spl_board_init(void)
> +{
> +	struct udevice *dev;
> +
> +	puts("Normal Boot\n");
> +
> +	uclass_find_first_device(UCLASS_CLK, &dev);
> +
> +	for (; dev; uclass_find_next_device(&dev)) {
> +		if (device_probe(dev))
> +			continue;

Is this correct that in the SPL you call probe on all UCLASS_CLK
devices registered for i.MX8?

> +	}
> +}
> +
> +#ifdef CONFIG_SPL_LOAD_FIT
> +int board_fit_config_name_match(const char *name)
> +{
> +	/* Just empty function now - can't decide what to choose */
> +	debug("%s: %s\n", __func__, name);
> +
> +	return 0;
> +}
> +#endif
> +
> +void board_init_f(ulong dummy)
> +{
> +	int ret;
> +
> +	arch_cpu_init();
> +
> +	init_uart_clk(1);
> +
> +	board_early_init_f();
> +
> +	timer_init();
> +
> +	preloader_console_init();
> +
> +	/* Clear the BSS. */
> +	memset(__bss_start, 0, __bss_end - __bss_start);
> +
> +	ret = spl_init();
> +	if (ret) {
> +		debug("spl_init() failed: %d\n", ret);
> +		hang();
> +	}
> +
> +	enable_tzc380();
> +
> +	/* DDR initialization */
> +	spl_dram_init();
> +
> +	board_init_r(NULL, 0);
> +}
> diff --git a/configs/imx8mn_ddr4_evk_defconfig
> b/configs/imx8mn_ddr4_evk_defconfig new file mode 100644
> index 0000000000..01e10fc427
> --- /dev/null
> +++ b/configs/imx8mn_ddr4_evk_defconfig
> @@ -0,0 +1,53 @@
> +CONFIG_ARM=y
> +CONFIG_ARCH_IMX8M=y
> +CONFIG_SYS_TEXT_BASE=0x40200000
> +CONFIG_SPL_GPIO_SUPPORT=y
> +CONFIG_SPL_LIBCOMMON_SUPPORT=y
> +CONFIG_SPL_LIBGENERIC_SUPPORT=y
> +CONFIG_SYS_MALLOC_F_LEN=0x6000
> +CONFIG_TARGET_IMX8MN_EVK=y
> +CONFIG_SPL_SERIAL_SUPPORT=y
> +CONFIG_SPL=y
> +CONFIG_IMX_ROMAPI_LOADADDR=0x48000000
> +CONFIG_FIT=y
> +CONFIG_FIT_EXTERNAL_OFFSET=0x3000
> +CONFIG_SPL_LOAD_FIT=y
> +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
> +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mn-ddr4.cfg"
> +CONFIG_DEFAULT_FDT_FILE="fsl-imx8mn-ddr4-evk.dtb"
> +CONFIG_SPL_TEXT_BASE=0x912000
> +CONFIG_SPL_BOARD_INIT=y
> +CONFIG_SPL_BOOTROM_SUPPORT=y
> +CONFIG_SPL_SEPARATE_BSS=y
> +CONFIG_SPL_I2C_SUPPORT=y
> +CONFIG_HUSH_PARSER=y
> +CONFIG_CMD_CLK=y
> +CONFIG_CMD_GPIO=y
> +CONFIG_CMD_I2C=y
> +CONFIG_CMD_CACHE=y
> +CONFIG_CMD_REGULATOR=y
> +CONFIG_CMD_EXT2=y
> +CONFIG_CMD_EXT4=y
> +CONFIG_CMD_EXT4_WRITE=y
> +CONFIG_CMD_FAT=y
> +CONFIG_OF_CONTROL=y
> +CONFIG_SPL_OF_CONTROL=y
> +CONFIG_DEFAULT_DEVICE_TREE="imx8mm-evk"
> +CONFIG_SPL_DM=y
> +CONFIG_SPL_CLK=y
> +CONFIG_CLK_IMX8MN=y
> +CONFIG_DM_GPIO=y
> +CONFIG_MXC_GPIO=y
> +CONFIG_DM_I2C=y
> +CONFIG_SYS_I2C_MXC=y
> +CONFIG_DM_MMC=y
> +CONFIG_PHYLIB=y
> +CONFIG_DM_ETH=y
> +CONFIG_PINCTRL=y
> +CONFIG_SPL_PINCTRL=y
> +CONFIG_PINCTRL_IMX8M=y
> +CONFIG_DM_REGULATOR=y
> +CONFIG_DM_REGULATOR_FIXED=y
> +CONFIG_DM_REGULATOR_GPIO=y
> +CONFIG_MXC_UART=y
> +CONFIG_DM_THERMAL=y

You could also from the beginning enable CONFIG_WDT and CONFIG_SYSRESET
(as i.MX6 already uses it).

> diff --git a/include/configs/imx8mn_evk.h
> b/include/configs/imx8mn_evk.h new file mode 100644
> index 0000000000..6ec8a2e362
> --- /dev/null
> +++ b/include/configs/imx8mn_evk.h
> @@ -0,0 +1,198 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright 2018 NXP
> + */
> +
> +#ifndef __IMX8MN_EVK_H
> +#define __IMX8MN_EVK_H
> +
> +#include <linux/sizes.h>
> +#include <asm/arch/imx-regs.h>
> +
> +#ifdef CONFIG_SECURE_BOOT
> +#define CONFIG_CSF_SIZE			0x2000 /* 8K region */
> +#endif
> +
> +#define CONFIG_SPL_MAX_SIZE		(148 * 1024)
> +#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
> +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
> +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300
> +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
> +#define CONFIG_SYS_UBOOT_BASE	\
> +	(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR *
> 512) +
> +#ifdef CONFIG_SPL_BUILD
> +/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
> +#define CONFIG_SPL_WATCHDOG_SUPPORT
> +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
> +#define CONFIG_SPL_POWER_SUPPORT
> +#define
> CONFIG_SPL_LDSCRIPT		"arch/arm/cpu/armv8/u-boot-spl.lds"
> +#define CONFIG_SPL_STACK		0x95fff0 +#define
> CONFIG_SPL_BSS_START_ADDR	0x00950000 +#define
> CONFIG_SPL_BSS_MAX_SIZE		0x2000	/* 8 KB */

Please fix globally -> replace 0x2000 -> SZ_8K from
include/linux/sizes.h

> +#define CONFIG_SYS_SPL_MALLOC_START	0x42200000 +#define
> CONFIG_SYS_SPL_MALLOC_SIZE	0x80000	/* 64 KB */ +#define
> CONFIG_SYS_ICACHE_OFF +#define CONFIG_SYS_DCACHE_OFF
> +
> +/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
> +#define CONFIG_MALLOC_F_ADDR		0x00940000
> +
> +/* For RAW image gives a error info not panic */
> +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
> +
> +#undef CONFIG_DM_MMC
> +#undef CONFIG_DM_PMIC
> +#undef CONFIG_DM_PMIC_PFUZE100
> +
> +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
> +
> +#endif
> +
> +#define CONFIG_REMAKE_ELF
> +
> +#define CONFIG_BOARD_EARLY_INIT_F
> +#define CONFIG_BOARD_POSTCLK_INIT
> +#define CONFIG_BOARD_LATE_INIT
> +
> +/* Flat Device Tree Definitions */
> +#define CONFIG_OF_BOARD_SETUP
> +
> +#undef CONFIG_CMD_EXPORTENV
> +#undef CONFIG_CMD_IMPORTENV
> +#undef CONFIG_CMD_IMLS
> +
> +#undef CONFIG_CMD_CRC32
> +#undef CONFIG_BOOTM_NETBSD
> +
> +/* Initial environment variables */
> +#define CONFIG_EXTRA_ENV_SETTINGS		\
> +	"script=boot.scr\0" \
> +	"image=Image\0" \
> +	"console=ttymxc1,115200
> earlycon=ec_imx6q,0x30890000,115200\0" \
> +	"fdt_addr=0x43000000\0"			\
> +	"fdt_high=0xffffffffffffffff\0"		\
> +	"boot_fdt=try\0" \
> +	"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
> +	"initrd_addr=0x43800000\0"		\
> +	"initrd_high=0xffffffffffffffff\0" \
> +	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
> +	"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
> +	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
> +	"mmcautodetect=yes\0" \
> +	"mmcargs=setenv bootargs console=${console}
> root=${mmcroot}\0 " \
> +	"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr}
> ${script};\0" \
> +	"bootscript=echo Running bootscript from mmc ...; " \
> +		"source\0" \
> +	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr}
> ${image}\0" \
> +	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr}
> ${fdt_file}\0" \
> +	"mmcboot=echo Booting from mmc ...; " \
> +		"run mmcargs; " \
> +		"if test ${boot_fdt} = yes || test ${boot_fdt} =
> try; then " \
> +			"if run loadfdt; then " \
> +				"booti ${loadaddr} - ${fdt_addr}; " \

Please correct me if I'm wrong, but why do you use 'booti' (and
presumably boot Image?).

Please use fitImage (in think that it is mature enough to be used for
new ports - other imx SoCs use it already for some time); 

It can be called as: bootm ${loadaddr}#conf@${fdt_conf}


> +			"else " \
> +				"echo WARN: Cannot load the DT; " \
> +			"fi; " \
> +		"else " \
> +			"echo wait for boot; " \
> +		"fi;\0" \
> +	"netargs=setenv bootargs console=${console} " \
> +		"root=/dev/nfs " \
> +		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
> +	"netboot=echo Booting from net ...; " \
> +		"run netargs;  " \
> +		"if test ${ip_dyn} = yes; then " \
> +			"setenv get_cmd dhcp; " \
> +		"else " \
> +			"setenv get_cmd tftp; " \
> +		"fi; " \
> +		"${get_cmd} ${loadaddr} ${image}; " \
> +		"if test ${boot_fdt} = yes || test ${boot_fdt} =
> try; then " \
> +			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then
> " \
> +				"booti ${loadaddr} - ${fdt_addr}; " \
> +			"else " \
> +				"echo WARN: Cannot load the DT; " \
> +			"fi; " \
> +		"else " \
> +			"booti; " \
> +		"fi;\0"
> +
> +#define CONFIG_BOOTCOMMAND \
> +	   "mmc dev ${mmcdev}; if mmc rescan; then " \
> +		   "if run loadbootscript; then " \
> +			   "run bootscript; " \
> +		   "else " \
> +			   "if run loadimage; then " \
> +				   "run mmcboot; " \
> +			   "else run netboot; " \
> +			   "fi; " \
> +		   "fi; " \
> +	   "else booti ${loadaddr} - ${fdt_addr}; fi"
> +
> +/* Link Definitions */
> +#define CONFIG_LOADADDR			0x40480000
> +
> +#define CONFIG_SYS_LOAD_ADDR           CONFIG_LOADADDR
> +
> +#define CONFIG_SYS_INIT_RAM_ADDR        0x40000000
> +#define CONFIG_SYS_INIT_RAM_SIZE        0x80000
> +#define CONFIG_SYS_INIT_SP_OFFSET \
> +	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
> +#define CONFIG_SYS_INIT_SP_ADDR \
> +	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
> +
> +#define CONFIG_ENV_OVERWRITE
> +#if defined(CONFIG_ENV_IS_IN_MMC)
> +#define CONFIG_ENV_OFFSET               (64 * SZ_64K)
> +#endif
> +#define CONFIG_ENV_SIZE			0x1000
> +#define CONFIG_SYS_MMC_ENV_DEV		0   /* USDHC2 */
> +#define CONFIG_MMCROOT			"/dev/mmcblk1p2"  /*
> USDHC2 */ +
> +/* Size of malloc() pool */
> +#define CONFIG_SYS_MALLOC_LEN		SZ_32M
> +
> +#define CONFIG_SYS_SDRAM_BASE           0x40000000
> +#define PHYS_SDRAM                      0x40000000
> +#define PHYS_SDRAM_SIZE			0x80000000 /* 2GB DDR
> */ +
> +#define CONFIG_SYS_MEMTEST_START    PHYS_SDRAM
> +#define CONFIG_SYS_MEMTEST_END      (CONFIG_SYS_MEMTEST_START +
> (PHYS_SDRAM_SIZE >> 1)) +
> +#define CONFIG_BAUDRATE			115200
> +
> +#define CONFIG_MXC_UART_BASE		UART2_BASE_ADDR
> +
> +/* Monitor Command Prompt */
> +#undef CONFIG_SYS_PROMPT
> +#define CONFIG_SYS_PROMPT		"u-boot=> "
> +#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
> +#define CONFIG_SYS_CBSIZE		2048
> +#define CONFIG_SYS_MAXARGS		64
> +#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
> +#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
> +					sizeof(CONFIG_SYS_PROMPT) +
> 16) +
> +#define CONFIG_IMX_BOOTAUX

Has the i.MX8 the use case for IMX_BOOTAUX - if not please remove it.

> +
> +/* USDHC */
> +#define CONFIG_CMD_MMC
> +#define CONFIG_FSL_ESDHC
> +#define CONFIG_FSL_USDHC
> +
> +#define CONFIG_SYS_FSL_USDHC_NUM	2
> +#define CONFIG_SYS_FSL_ESDHC_ADDR	0

Some of the above are in Kconfig.

> +
> +#define CONFIG_SUPPORT_EMMC_BOOT	/* eMMC specific */
> +#define CONFIG_SYS_MMC_IMG_LOAD_PART	1
> +
> +#define CONFIG_CMD_FUSE
> +
> +#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
> +#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
> +#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */

> +#define CONFIG_SYS_I2C_SPEED		100000

Those #defines (I2C related) are already supported in Kconfig. Please
use them.


Please review above defines and move to Kconfig.

> +
> +#define CONFIG_OF_SYSTEM_SETUP
> +#endif




Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma@denx.de
Peng Fan July 10, 2019, 10:05 a.m. UTC | #2
> Subject: Re: [U-Boot] [PATCH V2 51/51] imx: add i.MX8MN DDR4 board
> support
> 
[...]
> > +
> > MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x190
> 
> Those changes looks identical. Why do you need to change those lines?
> (Wrong formatting) ?

Wrongly added. Drop in V3.

> 
> >  		>;
> > +};
[...]
> 
> > diff --git a/arch/arm/dts/imx8mn-ddr4-evk.dts
> > b/arch/arm/dts/imx8mn-ddr4-evk.dts new file mode 100644
> > index 0000000000..9b2c1727a8
> > --- /dev/null
> > +++ b/arch/arm/dts/imx8mn-ddr4-evk.dts
> 
> DTS files shall be added in a separate commit, to avoid one very large
> one when you add the board.

Fix in V3.

> 
> > @@ -0,0 +1,221 @@
> > +	{ 0x3d400498, 0x03ff0000 },
> > +	{ 0x3d40049c, 0x01000e00 },
> > +	{ 0x3d4004a0, 0x03ff0000 },
> > +};
> 
> Isn't there auto training code for i.MX8 as it is for i.MX6Q?
> 
> For example:
> https://gitlab.denx.de/u-boot/u-boot/blob/master/arch/arm/mach-imx/mx6
> /ddr.c
> https://gitlab.denx.de/u-boot/u-boot/blob/master/arch/arm/mach-imx/ddr
> mc-vf610-calibration.c

The DDR FW will do auto training. The DDR controller is
complicated and different from i.MX6.


> 
> 
> > +
> > +/* PHY Initialize Configuration */
> > +struct dram_cfg_param ddr_ddrphy_cfg[] = {
> > +};
[....]
> > +
> 
> The list of binary data is quite impressive for i.MX8

There are many many many registers in the DDRC in i.MX8M needs
to configured.

> 
> > +struct dram_fsp_msg ddr_dram_fsp_msg[] = {
[..]
> > +{
> > +	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
> > +
> > +	imx_iomux_v3_setup_multiple_pads(wdog_pads,
> 
> Shouldn't those pins be configured via DTS/DM? As fair as I see this is
> the imx8mn_evk.c file (which seems not to be the SPL).

DM WDOG is not enabled here. Just use reset_cpu to do external reset

> 
> > ARRAY_SIZE(wdog_pads)); +
> > +	set_wdog_reset(wdog);
> > +
> > +	imx_iomux_v3_setup_multiple_pads(uart_pads,
> > ARRAY_SIZE(uart_pads)); +
> > +	init_uart_clk(1);
> 
> This also seems like not DM/DTS code.

We not enable DM UART.

> 
> > +
> > +	return 0;
> > +}
> > +
> > +#ifdef CONFIG_BOARD_POSTCLK_INIT
> > +int board_postclk_init(void)
> > +{
> > +	/* TODO */
> > +	return 0;
> > +}
> > +#endif
> > +
> > +int dram_init(void)
> > +{
> > +	/* rom_pointer[1] contains the size of TEE occupies */
> > +	if (rom_pointer[1])
> > +		gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1];
> > +	else
> > +		gd->ram_size = PHYS_SDRAM_SIZE;
> > +
> > +	return 0;
> > +}
> > +
> > +#ifdef CONFIG_OF_BOARD_SETUP
> > +int ft_board_setup(void *blob, bd_t *bd)
> > +{
> > +	return 0;
> > +}
> > +#endif
> > +
> > +int board_init(void)
> > +{
> > +	return 0;
> > +}
> > +
> > +int board_mmc_get_env_dev(int devno)
> > +{
> > +	return devno - 1;
> > +}
> 
> Shouldn't the number of mmc device be get via alias defined in DTS (or
> assigned automatically)?
> 
> What is the purpose of this function?

mmc_get_env_dev will call this function. devno is the controller index
inside SoC, however not every controller is enabled in a board.

> 
> > +
> > +int board_late_init(void)
> > +{
> > +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
> > +	env_set("board_name", "DDR4 EVK");
> > +	env_set("board_rev", "iMX8MN");
> > +#endif
> > +	return 0;
> > +}
> > diff --git a/board/freescale/imx8mn_evk/spl.c
> > b/board/freescale/imx8mn_evk/spl.c new file mode 100644
> > index 0000000000..aa5f37fde0
> > --- /dev/null
> > +++ b/board/freescale/imx8mn_evk/spl.c
> > @@ -0,0 +1,90 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright 2019 NXP
> > + */
> > +
> > +#include <common.h>
> > +#include <spl.h>
> > +#include <asm/io.h>
> > +#include <errno.h>
> > +#include <asm/arch/imx8mn_pins.h>
> > +#include <asm/arch/sys_proto.h>
> > +#include <asm/arch/clock.h>
> > +#include <asm/gpio.h>
> > +#include <asm/arch/ddr.h>
> > +#include <asm/mach-imx/boot_mode.h>
> > +#include <asm/mach-imx/gpio.h>
> > +#include <asm/mach-imx/iomux-v3.h>
> > +#include <asm/mach-imx/mxc_i2c.h>
> > +
> > +#include <dm/uclass.h>
> > +#include <dm/device.h>
> > +#include <dm/uclass-internal.h>
> > +#include <dm/device-internal.h>
> > +
> > +DECLARE_GLOBAL_DATA_PTR;
> > +
> > +int spl_board_boot_device(enum boot_device boot_dev_spl)
> > +{
> > +	return BOOT_DEVICE_BOOTROM;
> > +}
> > +
> > +void spl_dram_init(void)
> > +{
> > +	ddr_init(&dram_timing);
> > +}
> > +
> > +void spl_board_init(void)
> > +{
> > +	struct udevice *dev;
> > +
> > +	puts("Normal Boot\n");
> > +
> > +	uclass_find_first_device(UCLASS_CLK, &dev);
> > +
> > +	for (; dev; uclass_find_next_device(&dev)) {
> > +		if (device_probe(dev))
> > +			continue;
> 
> Is this correct that in the SPL you call probe on all UCLASS_CLK
> devices registered for i.MX8?

Any issue you forseen?

> 
> > +	}
> > +}
> > +
> > +#ifdef CONFIG_SPL_LOAD_FIT
> > +int board_fit_config_name_match(const char *name)
> > +{
> > +	/* Just empty function now - can't decide what to choose */
> > +	debug("%s: %s\n", __func__, name);
> > +
> > +	return 0;
> > +}
> > +#endif
> > +
> > +void board_init_f(ulong dummy)
> > +{
> > +	int ret;
> > +
> > +	arch_cpu_init();
> > +
> > +	init_uart_clk(1);
> > +
> > +	board_early_init_f();
> > +
> > +	timer_init();
> > +
> > +	preloader_console_init();
> > +
> > +	/* Clear the BSS. */
> > +	memset(__bss_start, 0, __bss_end - __bss_start);
> > +
> > +	ret = spl_init();
> > +	if (ret) {
> > +		debug("spl_init() failed: %d\n", ret);
> > +		hang();
> > +	}
> > +
> > +	enable_tzc380();
> > +
> > +	/* DDR initialization */
> > +	spl_dram_init();
> > +
> > +	board_init_r(NULL, 0);
> > +}
> > diff --git a/configs/imx8mn_ddr4_evk_defconfig
> > b/configs/imx8mn_ddr4_evk_defconfig new file mode 100644
> > index 0000000000..01e10fc427
> > --- /dev/null
> > +++ b/configs/imx8mn_ddr4_evk_defconfig
> > @@ -0,0 +1,53 @@
> > +CONFIG_ARM=y
> > +CONFIG_ARCH_IMX8M=y
> > +CONFIG_SYS_TEXT_BASE=0x40200000
> > +CONFIG_SPL_GPIO_SUPPORT=y
> > +CONFIG_SPL_LIBCOMMON_SUPPORT=y
> > +CONFIG_SPL_LIBGENERIC_SUPPORT=y
> > +CONFIG_SYS_MALLOC_F_LEN=0x6000
> > +CONFIG_TARGET_IMX8MN_EVK=y
> > +CONFIG_SPL_SERIAL_SUPPORT=y
> > +CONFIG_SPL=y
> > +CONFIG_IMX_ROMAPI_LOADADDR=0x48000000
> > +CONFIG_FIT=y
> > +CONFIG_FIT_EXTERNAL_OFFSET=0x3000
> > +CONFIG_SPL_LOAD_FIT=y
> > +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
> >
> +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m
> /imximage-8mn-ddr4.cfg"
> > +CONFIG_DEFAULT_FDT_FILE="fsl-imx8mn-ddr4-evk.dtb"
> > +CONFIG_SPL_TEXT_BASE=0x912000
> > +CONFIG_SPL_BOARD_INIT=y
> > +CONFIG_SPL_BOOTROM_SUPPORT=y
> > +CONFIG_SPL_SEPARATE_BSS=y
> > +CONFIG_SPL_I2C_SUPPORT=y
> > +CONFIG_HUSH_PARSER=y
> > +CONFIG_CMD_CLK=y
> > +CONFIG_CMD_GPIO=y
> > +CONFIG_CMD_I2C=y
> > +CONFIG_CMD_CACHE=y
> > +CONFIG_CMD_REGULATOR=y
> > +CONFIG_CMD_EXT2=y
> > +CONFIG_CMD_EXT4=y
> > +CONFIG_CMD_EXT4_WRITE=y
> > +CONFIG_CMD_FAT=y
> > +CONFIG_OF_CONTROL=y
> > +CONFIG_SPL_OF_CONTROL=y
> > +CONFIG_DEFAULT_DEVICE_TREE="imx8mm-evk"
> > +CONFIG_SPL_DM=y
> > +CONFIG_SPL_CLK=y
> > +CONFIG_CLK_IMX8MN=y
> > +CONFIG_DM_GPIO=y
> > +CONFIG_MXC_GPIO=y
> > +CONFIG_DM_I2C=y
> > +CONFIG_SYS_I2C_MXC=y
> > +CONFIG_DM_MMC=y
> > +CONFIG_PHYLIB=y
> > +CONFIG_DM_ETH=y
> > +CONFIG_PINCTRL=y
> > +CONFIG_SPL_PINCTRL=y
> > +CONFIG_PINCTRL_IMX8M=y
> > +CONFIG_DM_REGULATOR=y
> > +CONFIG_DM_REGULATOR_FIXED=y
> > +CONFIG_DM_REGULATOR_GPIO=y
> > +CONFIG_MXC_UART=y
> > +CONFIG_DM_THERMAL=y
> 
> You could also from the beginning enable CONFIG_WDT and
> CONFIG_SYSRESET
> (as i.MX6 already uses it).

I'll try.

> 
> > diff --git a/include/configs/imx8mn_evk.h
> > b/include/configs/imx8mn_evk.h new file mode 100644
> > index 0000000000..6ec8a2e362
> > --- /dev/null
> > +++ b/include/configs/imx8mn_evk.h
> > @@ -0,0 +1,198 @@
> > +/* SPDX-License-Identifier: GPL-2.0+ */
> > +/*
> > + * Copyright 2018 NXP
> > + */
> > +
> > +#ifndef __IMX8MN_EVK_H
> > +#define __IMX8MN_EVK_H
> > +
> > +#include <linux/sizes.h>
> > +#include <asm/arch/imx-regs.h>
> > +
> > +#ifdef CONFIG_SECURE_BOOT
> > +#define CONFIG_CSF_SIZE			0x2000 /* 8K region */
> > +#endif
> > +
> > +#define CONFIG_SPL_MAX_SIZE		(148 * 1024)
> > +#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
> > +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
> > +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300
> > +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
> > +#define CONFIG_SYS_UBOOT_BASE	\
> > +	(QSPI0_AMBA_BASE +
> CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR *
> > 512) +
> > +#ifdef CONFIG_SPL_BUILD
> > +/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
> > +#define CONFIG_SPL_WATCHDOG_SUPPORT
> > +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
> > +#define CONFIG_SPL_POWER_SUPPORT
> > +#define
> > CONFIG_SPL_LDSCRIPT		"arch/arm/cpu/armv8/u-boot-spl.lds"
> > +#define CONFIG_SPL_STACK		0x95fff0 +#define
> > CONFIG_SPL_BSS_START_ADDR	0x00950000 +#define
> > CONFIG_SPL_BSS_MAX_SIZE		0x2000	/* 8 KB */
> 
> Please fix globally -> replace 0x2000 -> SZ_8K from
> include/linux/sizes.h

Fix in V3.

> 
> > +#define CONFIG_SYS_SPL_MALLOC_START	0x42200000 +#define
> > CONFIG_SYS_SPL_MALLOC_SIZE	0x80000	/* 64 KB */ +#define
> > CONFIG_SYS_ICACHE_OFF +#define CONFIG_SYS_DCACHE_OFF
> > +
> > +/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
> > +#define CONFIG_MALLOC_F_ADDR		0x00940000
> > +
> > +/* For RAW image gives a error info not panic */
> > +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
> > +
> > +#undef CONFIG_DM_MMC
> > +#undef CONFIG_DM_PMIC
> > +#undef CONFIG_DM_PMIC_PFUZE100
> > +
> > +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
> > +
> > +#endif
> > +
> > +#define CONFIG_REMAKE_ELF
> > +
> > +#define CONFIG_BOARD_EARLY_INIT_F
> > +#define CONFIG_BOARD_POSTCLK_INIT
> > +#define CONFIG_BOARD_LATE_INIT
> > +
> > +/* Flat Device Tree Definitions */
> > +#define CONFIG_OF_BOARD_SETUP
> > +
> > +#undef CONFIG_CMD_EXPORTENV
> > +#undef CONFIG_CMD_IMPORTENV
> > +#undef CONFIG_CMD_IMLS
> > +
> > +#undef CONFIG_CMD_CRC32
> > +#undef CONFIG_BOOTM_NETBSD
> > +
> > +/* Initial environment variables */
> > +#define CONFIG_EXTRA_ENV_SETTINGS		\
> > +	"script=boot.scr\0" \
> > +	"image=Image\0" \
> > +	"console=ttymxc1,115200
> > earlycon=ec_imx6q,0x30890000,115200\0" \
> > +	"fdt_addr=0x43000000\0"			\
> > +	"fdt_high=0xffffffffffffffff\0"		\
> > +	"boot_fdt=try\0" \
> > +	"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
> > +	"initrd_addr=0x43800000\0"		\
> > +	"initrd_high=0xffffffffffffffff\0" \
> > +	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
> > +	"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
> > +	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
> > +	"mmcautodetect=yes\0" \
> > +	"mmcargs=setenv bootargs console=${console}
> > root=${mmcroot}\0 " \
> > +	"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr}
> > ${script};\0" \
> > +	"bootscript=echo Running bootscript from mmc ...; " \
> > +		"source\0" \
> > +	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr}
> > ${image}\0" \
> > +	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr}
> > ${fdt_file}\0" \
> > +	"mmcboot=echo Booting from mmc ...; " \
> > +		"run mmcargs; " \
> > +		"if test ${boot_fdt} = yes || test ${boot_fdt} =
> > try; then " \
> > +			"if run loadfdt; then " \
> > +				"booti ${loadaddr} - ${fdt_addr}; " \
> 
> Please correct me if I'm wrong, but why do you use 'booti' (and
> presumably boot Image?).
> 
> Please use fitImage (in think that it is mature enough to be used for
> new ports - other imx SoCs use it already for some time);
> 
> It can be called as: bootm ${loadaddr}#conf@${fdt_conf}

No. We not switch to FIT when uboot booting kernel.

> 
> 
> > +			"else " \
> > +				"echo WARN: Cannot load the DT; " \
> > +			"fi; " \
> > +		"else " \
> > +			"echo wait for boot; " \
> > +		"fi;\0" \
> > +	"netargs=setenv bootargs console=${console} " \
> > +		"root=/dev/nfs " \
> > +		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
> > +	"netboot=echo Booting from net ...; " \
> > +		"run netargs;  " \
> > +		"if test ${ip_dyn} = yes; then " \
> > +			"setenv get_cmd dhcp; " \
> > +		"else " \
> > +			"setenv get_cmd tftp; " \
> > +		"fi; " \
> > +		"${get_cmd} ${loadaddr} ${image}; " \
> > +		"if test ${boot_fdt} = yes || test ${boot_fdt} =
> > try; then " \
> > +			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then
> > " \
> > +				"booti ${loadaddr} - ${fdt_addr}; " \
> > +			"else " \
> > +				"echo WARN: Cannot load the DT; " \
> > +			"fi; " \
> > +		"else " \
> > +			"booti; " \
> > +		"fi;\0"
> > +
> > +#define CONFIG_BOOTCOMMAND \
> > +	   "mmc dev ${mmcdev}; if mmc rescan; then " \
> > +		   "if run loadbootscript; then " \
> > +			   "run bootscript; " \
> > +		   "else " \
> > +			   "if run loadimage; then " \
> > +				   "run mmcboot; " \
> > +			   "else run netboot; " \
> > +			   "fi; " \
> > +		   "fi; " \
> > +	   "else booti ${loadaddr} - ${fdt_addr}; fi"
> > +
> > +/* Link Definitions */
> > +#define CONFIG_LOADADDR			0x40480000
> > +
> > +#define CONFIG_SYS_LOAD_ADDR           CONFIG_LOADADDR
> > +
> > +#define CONFIG_SYS_INIT_RAM_ADDR        0x40000000
> > +#define CONFIG_SYS_INIT_RAM_SIZE        0x80000
> > +#define CONFIG_SYS_INIT_SP_OFFSET \
> > +	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
> > +#define CONFIG_SYS_INIT_SP_ADDR \
> > +	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
> > +
> > +#define CONFIG_ENV_OVERWRITE
> > +#if defined(CONFIG_ENV_IS_IN_MMC)
> > +#define CONFIG_ENV_OFFSET               (64 * SZ_64K)
> > +#endif
> > +#define CONFIG_ENV_SIZE			0x1000
> > +#define CONFIG_SYS_MMC_ENV_DEV		0   /* USDHC2 */
> > +#define CONFIG_MMCROOT			"/dev/mmcblk1p2"  /*
> > USDHC2 */ +
> > +/* Size of malloc() pool */
> > +#define CONFIG_SYS_MALLOC_LEN		SZ_32M
> > +
> > +#define CONFIG_SYS_SDRAM_BASE           0x40000000
> > +#define PHYS_SDRAM                      0x40000000
> > +#define PHYS_SDRAM_SIZE			0x80000000 /* 2GB DDR
> > */ +
> > +#define CONFIG_SYS_MEMTEST_START    PHYS_SDRAM
> > +#define CONFIG_SYS_MEMTEST_END
> (CONFIG_SYS_MEMTEST_START +
> > (PHYS_SDRAM_SIZE >> 1)) +
> > +#define CONFIG_BAUDRATE			115200
> > +
> > +#define CONFIG_MXC_UART_BASE		UART2_BASE_ADDR
> > +
> > +/* Monitor Command Prompt */
> > +#undef CONFIG_SYS_PROMPT
> > +#define CONFIG_SYS_PROMPT		"u-boot=> "
> > +#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
> > +#define CONFIG_SYS_CBSIZE		2048
> > +#define CONFIG_SYS_MAXARGS		64
> > +#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
> > +#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
> > +					sizeof(CONFIG_SYS_PROMPT) +
> > 16) +
> > +#define CONFIG_IMX_BOOTAUX
> 
> Has the i.MX8 the use case for IMX_BOOTAUX - if not please remove it.


i.MX8M use bootaux to kick M4

> 
> > +
> > +/* USDHC */
> > +#define CONFIG_CMD_MMC
> > +#define CONFIG_FSL_ESDHC
> > +#define CONFIG_FSL_USDHC
> > +
> > +#define CONFIG_SYS_FSL_USDHC_NUM	2
> > +#define CONFIG_SYS_FSL_ESDHC_ADDR	0
> 
> Some of the above are in Kconfig.
> 
> > +
> > +#define CONFIG_SUPPORT_EMMC_BOOT	/* eMMC specific */
> > +#define CONFIG_SYS_MMC_IMG_LOAD_PART	1
> > +
> > +#define CONFIG_CMD_FUSE
> > +
> > +#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
> > +#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
> > +#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
> 
> > +#define CONFIG_SYS_I2C_SPEED		100000
> 
> Those #defines (I2C related) are already supported in Kconfig. Please
> use them.
> 
> 
> Please review above defines and move to Kconfig.

Sure.

Thanks,
Peng.

> 
> > +
> > +#define CONFIG_OF_SYSTEM_SETUP
> > +#endif
> 
> 
> 
> 
> Best regards,
> 
> Lukasz Majewski
> 
> --
> 
> DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email:
> lukma@denx.de
Lukasz Majewski July 10, 2019, 12:18 p.m. UTC | #3
Hi Peng,

> > Subject: Re: [U-Boot] [PATCH V2 51/51] imx: add i.MX8MN DDR4 board
> > support
> >   
> [...]
> > > +
> > > MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x190  
> > 
> > Those changes looks identical. Why do you need to change those
> > lines? (Wrong formatting) ?  
> 
> Wrongly added. Drop in V3.
> 
> >   
> > >  		>;  
> > > +};  
> [...]
> >   
> > > diff --git a/arch/arm/dts/imx8mn-ddr4-evk.dts
> > > b/arch/arm/dts/imx8mn-ddr4-evk.dts new file mode 100644
> > > index 0000000000..9b2c1727a8
> > > --- /dev/null
> > > +++ b/arch/arm/dts/imx8mn-ddr4-evk.dts  
> > 
> > DTS files shall be added in a separate commit, to avoid one very
> > large one when you add the board.  
> 
> Fix in V3.
> 
> >   
> > > @@ -0,0 +1,221 @@
> > > +	{ 0x3d400498, 0x03ff0000 },
> > > +	{ 0x3d40049c, 0x01000e00 },
> > > +	{ 0x3d4004a0, 0x03ff0000 },
> > > +};  
> > 
> > Isn't there auto training code for i.MX8 as it is for i.MX6Q?
> > 
> > For example:
> > https://gitlab.denx.de/u-boot/u-boot/blob/master/arch/arm/mach-imx/mx6
> > /ddr.c
> > https://gitlab.denx.de/u-boot/u-boot/blob/master/arch/arm/mach-imx/ddr
> > mc-vf610-calibration.c  
> 
> The DDR FW will do auto training. 

Shouldn't there be any code to assist the training itself ?

> The DDR controller is
> complicated and different from i.MX6.

I guess that it has some capabilities to do the training in HW, the SW
only needs to feed input data and maybe start the process and check
results.

> 
> 
> > 
> >   
> > > +
> > > +/* PHY Initialize Configuration */
> > > +struct dram_cfg_param ddr_ddrphy_cfg[] = {
> > > +};  
> [....]
> > > +  
> > 
> > The list of binary data is quite impressive for i.MX8  
> 
> There are many many many registers in the DDRC in i.MX8M needs
> to configured.

First code for i.MX6 looked in a similar way. And after some time it
turned out that it could be written in C, not as a table of binary
blobs.

Is here also the similar situation?

Or to ask differently - isn't it possible to explain what your are
changing and for what purpose? 

> 
> >   
> > > +struct dram_fsp_msg ddr_dram_fsp_msg[] = {  
> [..]
> > > +{
> > > +	struct wdog_regs *wdog = (struct wdog_regs
> > > *)WDOG1_BASE_ADDR; +
> > > +	imx_iomux_v3_setup_multiple_pads(wdog_pads,  
> > 
> > Shouldn't those pins be configured via DTS/DM? As fair as I see
> > this is the imx8mn_evk.c file (which seems not to be the SPL).  
> 
> DM WDOG is not enabled here. 

If it is not enabled then the code shall be removed.

> Just use reset_cpu to do external reset

You shall use SYSRESET for that.

> 
> >   
> > > ARRAY_SIZE(wdog_pads)); +
> > > +	set_wdog_reset(wdog);
> > > +
> > > +	imx_iomux_v3_setup_multiple_pads(uart_pads,
> > > ARRAY_SIZE(uart_pads)); +
> > > +	init_uart_clk(1);  
> > 
> > This also seems like not DM/DTS code.  
> 
> We not enable DM UART.

This is u-boot proper, so DM UART shall be enabled.

> 
> >   
> > > +
> > > +	return 0;
> > > +}
> > > +
> > > +#ifdef CONFIG_BOARD_POSTCLK_INIT
> > > +int board_postclk_init(void)
> > > +{
> > > +	/* TODO */
> > > +	return 0;
> > > +}
> > > +#endif
> > > +
> > > +int dram_init(void)
> > > +{
> > > +	/* rom_pointer[1] contains the size of TEE occupies */
> > > +	if (rom_pointer[1])
> > > +		gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1];
> > > +	else
> > > +		gd->ram_size = PHYS_SDRAM_SIZE;
> > > +
> > > +	return 0;
> > > +}
> > > +
> > > +#ifdef CONFIG_OF_BOARD_SETUP
> > > +int ft_board_setup(void *blob, bd_t *bd)
> > > +{
> > > +	return 0;
> > > +}
> > > +#endif
> > > +
> > > +int board_init(void)
> > > +{
> > > +	return 0;
> > > +}
> > > +
> > > +int board_mmc_get_env_dev(int devno)
> > > +{
> > > +	return devno - 1;
> > > +}  
> > 
> > Shouldn't the number of mmc device be get via alias defined in DTS
> > (or assigned automatically)?
> > 
> > What is the purpose of this function?  
> 
> mmc_get_env_dev will call this function. devno is the controller index

Why do you need the index if you have DM_MMC enabled? The struct device
shall be enough to perform all the necessary operations.

> inside SoC, however not every controller is enabled in a board.

I may be wrong, but this shall not be needed in DM_MMC supporting board.

> 
> >   
> > > +
> > > +int board_late_init(void)
> > > +{
> > > +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
> > > +	env_set("board_name", "DDR4 EVK");
> > > +	env_set("board_rev", "iMX8MN");
> > > +#endif
> > > +	return 0;
> > > +}
> > > diff --git a/board/freescale/imx8mn_evk/spl.c
> > > b/board/freescale/imx8mn_evk/spl.c new file mode 100644
> > > index 0000000000..aa5f37fde0
> > > --- /dev/null
> > > +++ b/board/freescale/imx8mn_evk/spl.c
> > > @@ -0,0 +1,90 @@
> > > +// SPDX-License-Identifier: GPL-2.0+
> > > +/*
> > > + * Copyright 2019 NXP
> > > + */
> > > +
> > > +#include <common.h>
> > > +#include <spl.h>
> > > +#include <asm/io.h>
> > > +#include <errno.h>
> > > +#include <asm/arch/imx8mn_pins.h>
> > > +#include <asm/arch/sys_proto.h>
> > > +#include <asm/arch/clock.h>
> > > +#include <asm/gpio.h>
> > > +#include <asm/arch/ddr.h>
> > > +#include <asm/mach-imx/boot_mode.h>
> > > +#include <asm/mach-imx/gpio.h>
> > > +#include <asm/mach-imx/iomux-v3.h>
> > > +#include <asm/mach-imx/mxc_i2c.h>
> > > +
> > > +#include <dm/uclass.h>
> > > +#include <dm/device.h>
> > > +#include <dm/uclass-internal.h>
> > > +#include <dm/device-internal.h>
> > > +
> > > +DECLARE_GLOBAL_DATA_PTR;
> > > +
> > > +int spl_board_boot_device(enum boot_device boot_dev_spl)
> > > +{
> > > +	return BOOT_DEVICE_BOOTROM;
> > > +}
> > > +
> > > +void spl_dram_init(void)
> > > +{
> > > +	ddr_init(&dram_timing);
> > > +}
> > > +
> > > +void spl_board_init(void)
> > > +{
> > > +	struct udevice *dev;
> > > +
> > > +	puts("Normal Boot\n");
> > > +
> > > +	uclass_find_first_device(UCLASS_CLK, &dev);
> > > +
> > > +	for (; dev; uclass_find_next_device(&dev)) {
> > > +		if (device_probe(dev))
> > > +			continue;  
> > 
> > Is this correct that in the SPL you call probe on all UCLASS_CLK
> > devices registered for i.MX8?  
> 
> Any issue you forseen?

It is just identical to what CCF is doing :-)

> 
> >   
> > > +	}
> > > +}
> > > +
> > > +#ifdef CONFIG_SPL_LOAD_FIT
> > > +int board_fit_config_name_match(const char *name)
> > > +{
> > > +	/* Just empty function now - can't decide what to choose
> > > */
> > > +	debug("%s: %s\n", __func__, name);
> > > +
> > > +	return 0;
> > > +}
> > > +#endif
> > > +
> > > +void board_init_f(ulong dummy)
> > > +{
> > > +	int ret;
> > > +
> > > +	arch_cpu_init();
> > > +
> > > +	init_uart_clk(1);
> > > +
> > > +	board_early_init_f();
> > > +
> > > +	timer_init();
> > > +
> > > +	preloader_console_init();
> > > +
> > > +	/* Clear the BSS. */
> > > +	memset(__bss_start, 0, __bss_end - __bss_start);
> > > +
> > > +	ret = spl_init();
> > > +	if (ret) {
> > > +		debug("spl_init() failed: %d\n", ret);
> > > +		hang();
> > > +	}
> > > +
> > > +	enable_tzc380();
> > > +
> > > +	/* DDR initialization */
> > > +	spl_dram_init();
> > > +
> > > +	board_init_r(NULL, 0);
> > > +}
> > > diff --git a/configs/imx8mn_ddr4_evk_defconfig
> > > b/configs/imx8mn_ddr4_evk_defconfig new file mode 100644
> > > index 0000000000..01e10fc427
> > > --- /dev/null
> > > +++ b/configs/imx8mn_ddr4_evk_defconfig
> > > @@ -0,0 +1,53 @@
> > > +CONFIG_ARM=y
> > > +CONFIG_ARCH_IMX8M=y
> > > +CONFIG_SYS_TEXT_BASE=0x40200000
> > > +CONFIG_SPL_GPIO_SUPPORT=y
> > > +CONFIG_SPL_LIBCOMMON_SUPPORT=y
> > > +CONFIG_SPL_LIBGENERIC_SUPPORT=y
> > > +CONFIG_SYS_MALLOC_F_LEN=0x6000
> > > +CONFIG_TARGET_IMX8MN_EVK=y
> > > +CONFIG_SPL_SERIAL_SUPPORT=y
> > > +CONFIG_SPL=y
> > > +CONFIG_IMX_ROMAPI_LOADADDR=0x48000000
> > > +CONFIG_FIT=y
> > > +CONFIG_FIT_EXTERNAL_OFFSET=0x3000
> > > +CONFIG_SPL_LOAD_FIT=y
> > > +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
> > >  
> > +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m
> > /imximage-8mn-ddr4.cfg"  
> > > +CONFIG_DEFAULT_FDT_FILE="fsl-imx8mn-ddr4-evk.dtb"
> > > +CONFIG_SPL_TEXT_BASE=0x912000
> > > +CONFIG_SPL_BOARD_INIT=y
> > > +CONFIG_SPL_BOOTROM_SUPPORT=y
> > > +CONFIG_SPL_SEPARATE_BSS=y
> > > +CONFIG_SPL_I2C_SUPPORT=y
> > > +CONFIG_HUSH_PARSER=y
> > > +CONFIG_CMD_CLK=y
> > > +CONFIG_CMD_GPIO=y
> > > +CONFIG_CMD_I2C=y
> > > +CONFIG_CMD_CACHE=y
> > > +CONFIG_CMD_REGULATOR=y
> > > +CONFIG_CMD_EXT2=y
> > > +CONFIG_CMD_EXT4=y
> > > +CONFIG_CMD_EXT4_WRITE=y
> > > +CONFIG_CMD_FAT=y
> > > +CONFIG_OF_CONTROL=y
> > > +CONFIG_SPL_OF_CONTROL=y
> > > +CONFIG_DEFAULT_DEVICE_TREE="imx8mm-evk"
> > > +CONFIG_SPL_DM=y
> > > +CONFIG_SPL_CLK=y
> > > +CONFIG_CLK_IMX8MN=y
> > > +CONFIG_DM_GPIO=y
> > > +CONFIG_MXC_GPIO=y
> > > +CONFIG_DM_I2C=y
> > > +CONFIG_SYS_I2C_MXC=y
> > > +CONFIG_DM_MMC=y
> > > +CONFIG_PHYLIB=y
> > > +CONFIG_DM_ETH=y
> > > +CONFIG_PINCTRL=y
> > > +CONFIG_SPL_PINCTRL=y
> > > +CONFIG_PINCTRL_IMX8M=y
> > > +CONFIG_DM_REGULATOR=y
> > > +CONFIG_DM_REGULATOR_FIXED=y
> > > +CONFIG_DM_REGULATOR_GPIO=y
> > > +CONFIG_MXC_UART=y
> > > +CONFIG_DM_THERMAL=y  
> > 
> > You could also from the beginning enable CONFIG_WDT and
> > CONFIG_SYSRESET
> > (as i.MX6 already uses it).  
> 
> I'll try.
> 
> >   
> > > diff --git a/include/configs/imx8mn_evk.h
> > > b/include/configs/imx8mn_evk.h new file mode 100644
> > > index 0000000000..6ec8a2e362
> > > --- /dev/null
> > > +++ b/include/configs/imx8mn_evk.h
> > > @@ -0,0 +1,198 @@
> > > +/* SPDX-License-Identifier: GPL-2.0+ */
> > > +/*
> > > + * Copyright 2018 NXP
> > > + */
> > > +
> > > +#ifndef __IMX8MN_EVK_H
> > > +#define __IMX8MN_EVK_H
> > > +
> > > +#include <linux/sizes.h>
> > > +#include <asm/arch/imx-regs.h>
> > > +
> > > +#ifdef CONFIG_SECURE_BOOT
> > > +#define CONFIG_CSF_SIZE			0x2000 /* 8K
> > > region */ +#endif
> > > +
> > > +#define CONFIG_SPL_MAX_SIZE		(148 * 1024)
> > > +#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
> > > +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
> > > +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300
> > > +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
> > > +#define CONFIG_SYS_UBOOT_BASE	\
> > > +	(QSPI0_AMBA_BASE +  
> > CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR *  
> > > 512) +
> > > +#ifdef CONFIG_SPL_BUILD
> > > +/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
> > > +#define CONFIG_SPL_WATCHDOG_SUPPORT
> > > +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
> > > +#define CONFIG_SPL_POWER_SUPPORT
> > > +#define
> > > CONFIG_SPL_LDSCRIPT		"arch/arm/cpu/armv8/u-boot-spl.lds"
> > > +#define CONFIG_SPL_STACK		0x95fff0 +#define
> > > CONFIG_SPL_BSS_START_ADDR	0x00950000 +#define
> > > CONFIG_SPL_BSS_MAX_SIZE		0x2000	/* 8 KB */  
> > 
> > Please fix globally -> replace 0x2000 -> SZ_8K from
> > include/linux/sizes.h  
> 
> Fix in V3.
> 
> >   
> > > +#define CONFIG_SYS_SPL_MALLOC_START	0x42200000 +#define
> > > CONFIG_SYS_SPL_MALLOC_SIZE	0x80000	/* 64 KB */
> > > +#define CONFIG_SYS_ICACHE_OFF +#define CONFIG_SYS_DCACHE_OFF
> > > +
> > > +/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
> > > +#define CONFIG_MALLOC_F_ADDR		0x00940000
> > > +
> > > +/* For RAW image gives a error info not panic */
> > > +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
> > > +
> > > +#undef CONFIG_DM_MMC
> > > +#undef CONFIG_DM_PMIC
> > > +#undef CONFIG_DM_PMIC_PFUZE100
> > > +
> > > +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
> > > +
> > > +#endif
> > > +
> > > +#define CONFIG_REMAKE_ELF
> > > +
> > > +#define CONFIG_BOARD_EARLY_INIT_F
> > > +#define CONFIG_BOARD_POSTCLK_INIT
> > > +#define CONFIG_BOARD_LATE_INIT
> > > +
> > > +/* Flat Device Tree Definitions */
> > > +#define CONFIG_OF_BOARD_SETUP
> > > +
> > > +#undef CONFIG_CMD_EXPORTENV
> > > +#undef CONFIG_CMD_IMPORTENV
> > > +#undef CONFIG_CMD_IMLS
> > > +
> > > +#undef CONFIG_CMD_CRC32
> > > +#undef CONFIG_BOOTM_NETBSD
> > > +
> > > +/* Initial environment variables */
> > > +#define CONFIG_EXTRA_ENV_SETTINGS		\
> > > +	"script=boot.scr\0" \
> > > +	"image=Image\0" \
> > > +	"console=ttymxc1,115200
> > > earlycon=ec_imx6q,0x30890000,115200\0" \
> > > +	"fdt_addr=0x43000000\0"			\
> > > +	"fdt_high=0xffffffffffffffff\0"		\
> > > +	"boot_fdt=try\0" \
> > > +	"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
> > > +	"initrd_addr=0x43800000\0"		\
> > > +	"initrd_high=0xffffffffffffffff\0" \
> > > +	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
> > > +	"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART)
> > > "\0" \
> > > +	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
> > > +	"mmcautodetect=yes\0" \
> > > +	"mmcargs=setenv bootargs console=${console}
> > > root=${mmcroot}\0 " \
> > > +	"loadbootscript=fatload mmc ${mmcdev}:${mmcpart}
> > > ${loadaddr} ${script};\0" \
> > > +	"bootscript=echo Running bootscript from mmc ...; " \
> > > +		"source\0" \
> > > +	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr}
> > > ${image}\0" \
> > > +	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr}
> > > ${fdt_file}\0" \
> > > +	"mmcboot=echo Booting from mmc ...; " \
> > > +		"run mmcargs; " \
> > > +		"if test ${boot_fdt} = yes || test ${boot_fdt} =
> > > try; then " \
> > > +			"if run loadfdt; then " \
> > > +				"booti ${loadaddr} -
> > > ${fdt_addr}; " \  
> > 
> > Please correct me if I'm wrong, but why do you use 'booti' (and
> > presumably boot Image?).
> > 
> > Please use fitImage (in think that it is mature enough to be used
> > for new ports - other imx SoCs use it already for some time);
> > 
> > It can be called as: bootm ${loadaddr}#conf@${fdt_conf}  
> 
> No. We not switch to FIT when uboot booting kernel.

This is strange. I can understand your objection to FitImage when you
wrap u-boot (to allow security IP block to calculate the checksum
effectively as it needs the proper image format).

However, I don't see any issues why you cannot use fitImage for booting
plain kernel.

Are there any technical difficulties for doing that? Do you have any
extra requirements ?

> 
> > 
> >   
> > > +			"else " \
> > > +				"echo WARN: Cannot load the DT;
> > > " \
> > > +			"fi; " \
> > > +		"else " \
> > > +			"echo wait for boot; " \
> > > +		"fi;\0" \
> > > +	"netargs=setenv bootargs console=${console} " \
> > > +		"root=/dev/nfs " \
> > > +		"ip=dhcp
> > > nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
> > > +	"netboot=echo Booting from net ...; " \
> > > +		"run netargs;  " \
> > > +		"if test ${ip_dyn} = yes; then " \
> > > +			"setenv get_cmd dhcp; " \
> > > +		"else " \
> > > +			"setenv get_cmd tftp; " \
> > > +		"fi; " \
> > > +		"${get_cmd} ${loadaddr} ${image}; " \
> > > +		"if test ${boot_fdt} = yes || test ${boot_fdt} =
> > > try; then " \
> > > +			"if ${get_cmd} ${fdt_addr} ${fdt_file};
> > > then " \
> > > +				"booti ${loadaddr} -
> > > ${fdt_addr}; " \
> > > +			"else " \
> > > +				"echo WARN: Cannot load the DT;
> > > " \
> > > +			"fi; " \
> > > +		"else " \
> > > +			"booti; " \
> > > +		"fi;\0"
> > > +
> > > +#define CONFIG_BOOTCOMMAND \
> > > +	   "mmc dev ${mmcdev}; if mmc rescan; then " \
> > > +		   "if run loadbootscript; then " \
> > > +			   "run bootscript; " \
> > > +		   "else " \
> > > +			   "if run loadimage; then " \
> > > +				   "run mmcboot; " \
> > > +			   "else run netboot; " \
> > > +			   "fi; " \
> > > +		   "fi; " \
> > > +	   "else booti ${loadaddr} - ${fdt_addr}; fi"
> > > +
> > > +/* Link Definitions */
> > > +#define CONFIG_LOADADDR			0x40480000
> > > +
> > > +#define CONFIG_SYS_LOAD_ADDR           CONFIG_LOADADDR
> > > +
> > > +#define CONFIG_SYS_INIT_RAM_ADDR        0x40000000
> > > +#define CONFIG_SYS_INIT_RAM_SIZE        0x80000
> > > +#define CONFIG_SYS_INIT_SP_OFFSET \
> > > +	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
> > > +#define CONFIG_SYS_INIT_SP_ADDR \
> > > +	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
> > > +
> > > +#define CONFIG_ENV_OVERWRITE
> > > +#if defined(CONFIG_ENV_IS_IN_MMC)
> > > +#define CONFIG_ENV_OFFSET               (64 * SZ_64K)
> > > +#endif
> > > +#define CONFIG_ENV_SIZE			0x1000
> > > +#define CONFIG_SYS_MMC_ENV_DEV		0   /* USDHC2 */
> > > +#define
> > > CONFIG_MMCROOT			"/dev/mmcblk1p2"  /* USDHC2
> > > */ + +/* Size of malloc() pool */
> > > +#define CONFIG_SYS_MALLOC_LEN		SZ_32M
> > > +
> > > +#define CONFIG_SYS_SDRAM_BASE           0x40000000
> > > +#define PHYS_SDRAM                      0x40000000
> > > +#define PHYS_SDRAM_SIZE			0x80000000 /* 2GB
> > > DDR */ +
> > > +#define CONFIG_SYS_MEMTEST_START    PHYS_SDRAM
> > > +#define CONFIG_SYS_MEMTEST_END  
> > (CONFIG_SYS_MEMTEST_START +  
> > > (PHYS_SDRAM_SIZE >> 1)) +
> > > +#define CONFIG_BAUDRATE			115200
> > > +
> > > +#define CONFIG_MXC_UART_BASE		UART2_BASE_ADDR
> > > +
> > > +/* Monitor Command Prompt */
> > > +#undef CONFIG_SYS_PROMPT
> > > +#define CONFIG_SYS_PROMPT		"u-boot=> "
> > > +#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
> > > +#define CONFIG_SYS_CBSIZE		2048
> > > +#define CONFIG_SYS_MAXARGS		64
> > > +#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
> > > +#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
> > > +
> > > sizeof(CONFIG_SYS_PROMPT) + 16) +
> > > +#define CONFIG_IMX_BOOTAUX  
> > 
> > Has the i.MX8 the use case for IMX_BOOTAUX - if not please remove
> > it.  
> 
> 
> i.MX8M use bootaux to kick M4

Ok.

> 
> >   
> > > +
> > > +/* USDHC */
> > > +#define CONFIG_CMD_MMC
> > > +#define CONFIG_FSL_ESDHC
> > > +#define CONFIG_FSL_USDHC
> > > +
> > > +#define CONFIG_SYS_FSL_USDHC_NUM	2
> > > +#define CONFIG_SYS_FSL_ESDHC_ADDR	0  
> > 
> > Some of the above are in Kconfig.
> >   
> > > +
> > > +#define CONFIG_SUPPORT_EMMC_BOOT	/* eMMC specific */
> > > +#define CONFIG_SYS_MMC_IMG_LOAD_PART	1
> > > +
> > > +#define CONFIG_CMD_FUSE
> > > +
> > > +#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus
> > > 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2		/* enable
> > > I2C bus 2 */ +#define CONFIG_SYS_I2C_MXC_I2C3		/*
> > > enable I2C bus 3 */  
> >   
> > > +#define CONFIG_SYS_I2C_SPEED		100000  
> > 
> > Those #defines (I2C related) are already supported in Kconfig.
> > Please use them.
> > 
> > 
> > Please review above defines and move to Kconfig.  
> 
> Sure.
> 
> Thanks,
> Peng.
> 
> >   
> > > +
> > > +#define CONFIG_OF_SYSTEM_SETUP
> > > +#endif  
> > 
> > 
> > 
> > 
> > Best regards,
> > 
> > Lukasz Majewski
> > 
> > --
> > 
> > DENX Software Engineering GmbH,      Managing Director: Wolfgang
> > Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell,
> > Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email:
> > lukma@denx.de  




Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma@denx.de

Patch
diff mbox series

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 8b7822cd99..e262880b79 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -617,7 +617,8 @@  dtb-$(CONFIG_ARCH_IMX8) += \
 	fsl-imx8qxp-mek.dtb
 
 dtb-$(CONFIG_ARCH_IMX8M) += fsl-imx8mq-evk.dtb \
-	imx8mm-evk.dtb
+	imx8mm-evk.dtb \
+	imx8mn-ddr4-evk.dtb
 
 dtb-$(CONFIG_RCAR_GEN2) += \
 	r8a7790-lager-u-boot.dtb \
diff --git a/arch/arm/dts/imx8mm-evk.dts b/arch/arm/dts/imx8mm-evk.dts
index 2d5d89475b..1e8b10a965 100644
--- a/arch/arm/dts/imx8mm-evk.dts
+++ b/arch/arm/dts/imx8mm-evk.dts
@@ -191,7 +191,7 @@ 
 			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d0
 			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d0
 			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d0
-			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 		0x190
+			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x190
 		>;
 	};
 
@@ -207,7 +207,7 @@ 
 			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d4
 			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d4
 			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d4
-			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 		0x194
+			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x194
 		>;
 	};
 
@@ -223,7 +223,7 @@ 
 			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d6
 			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d6
 			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d6
-			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 		0x196
+			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x196
 		>;
 	};
 
diff --git a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
new file mode 100644
index 0000000000..8d61597e0c
--- /dev/null
+++ b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
@@ -0,0 +1,92 @@ 
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+&{/soc@0} {
+	u-boot,dm-pre-reloc;
+	u-boot,dm-spl;
+};
+
+&clk {
+	u-boot,dm-spl;
+	u-boot,dm-pre-reloc;
+};
+
+&osc_24m {
+	u-boot,dm-spl;
+	u-boot,dm-pre-reloc;
+};
+
+&aips1 {
+	u-boot,dm-spl;
+	u-boot,dm-pre-reloc;
+};
+
+&aips2 {
+	u-boot,dm-spl;
+};
+
+&aips3 {
+	u-boot,dm-spl;
+};
+
+&iomuxc {
+	u-boot,dm-spl;
+};
+
+&pinctrl_reg_usdhc2_vmmc {
+	u-boot,dm-spl;
+};
+
+&pinctrl_uart2 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2_gpio {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc3 {
+	u-boot,dm-spl;
+};
+
+&gpio1 {
+	u-boot,dm-spl;
+};
+
+&gpio2 {
+	u-boot,dm-spl;
+};
+
+&gpio3 {
+	u-boot,dm-spl;
+};
+
+&gpio4 {
+	u-boot,dm-spl;
+};
+
+&gpio5 {
+	u-boot,dm-spl;
+};
+
+&uart2 {
+	u-boot,dm-spl;
+};
+
+&usdhc1 {
+	u-boot,dm-spl;
+};
+
+&usdhc2 {
+	u-boot,dm-spl;
+};
+
+&usdhc3 {
+	u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/imx8mn-ddr4-evk.dts b/arch/arm/dts/imx8mn-ddr4-evk.dts
new file mode 100644
index 0000000000..9b2c1727a8
--- /dev/null
+++ b/arch/arm/dts/imx8mn-ddr4-evk.dts
@@ -0,0 +1,221 @@ 
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2019 NXP
+ */
+
+/dts-v1/;
+
+#include "imx8mn.dtsi"
+
+/ {
+	model = "NXP i.MX8MNano DDR4 EVK board";
+	compatible = "fsl,imx8mn-ddr4-evk", "fsl,imx8mn";
+
+	chosen {
+		stdout-path = &uart2;
+	};
+
+	reg_usdhc2_vmmc: regulator-usdhc2 {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
+		regulator-name = "VSD_3V3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+
+	pinctrl_fec1: fec1grp {
+		fsl,pins = <
+			MX8MN_IOMUXC_ENET_MDC_ENET1_MDC		0x3
+			MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO	0x3
+			MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3	0x1f
+			MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2	0x1f
+			MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1	0x1f
+			MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0	0x1f
+			MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3	0x91
+			MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2	0x91
+			MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1	0x91
+			MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0	0x91
+			MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC	0x1f
+			MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC	0x91
+			MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
+			MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
+			MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22	0x19
+		>;
+	};
+
+	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
+		fsl,pins = <
+			MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41
+		>;
+	};
+
+	pinctrl_uart2: uart2grp {
+		fsl,pins = <
+			MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX	0x140
+			MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX	0x140
+		>;
+	};
+
+	pinctrl_usdhc2_gpio: usdhc2grpgpio {
+		fsl,pins = <
+			MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15	0x1c4
+		>;
+	};
+
+	pinctrl_usdhc2: usdhc2grp {
+		fsl,pins = <
+			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK		0x190
+			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d0
+			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0
+			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0
+			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0
+			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0
+			MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
+		>;
+	};
+
+	pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+		fsl,pins = <
+			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK		0x194
+			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4
+			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4
+			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4
+			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4
+			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4
+			MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
+		>;
+	};
+
+	pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+		fsl,pins = <
+			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK		0x196
+			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d6
+			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6
+			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6
+			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6
+			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6
+			MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
+		>;
+	};
+
+	pinctrl_usdhc3: usdhc3grp {
+		fsl,pins = <
+			MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK		0x40000190
+			MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d0
+			MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d0
+			MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d0
+			MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d0
+			MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d0
+			MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d0
+			MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d0
+			MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d0
+			MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d0
+			MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x190
+		>;
+	};
+
+	pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
+		fsl,pins = <
+			MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK		0x40000194
+			MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d4
+			MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d4
+			MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d4
+			MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d4
+			MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d4
+			MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d4
+			MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d4
+			MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d4
+			MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d4
+			MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x194
+		>;
+	};
+
+	pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
+		fsl,pins = <
+			MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK		0x40000196
+			MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d6
+			MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d6
+			MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d6
+			MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d6
+			MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d6
+			MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d6
+			MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d6
+			MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d6
+			MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d6
+			MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x196
+		>;
+	};
+
+	pinctrl_wdog: wdoggrp {
+		fsl,pins = <
+			MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B		0xc6
+		>;
+	};
+};
+
+&fec1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fec1>;
+	phy-mode = "rgmii-id";
+	phy-handle = <&ethphy0>;
+	fsl,magic-packet;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy0: ethernet-phy@0 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <0>;
+			at803x,led-act-blind-workaround;
+			at803x,eee-disabled;
+			at803x,vddio-1p8v;
+		};
+	};
+};
+
+&snvs_pwrkey {
+	status = "okay";
+};
+
+&uart2 { /* console */
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart2>;
+	status = "okay";
+};
+
+&usdhc2 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+	cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
+	bus-width = <4>;
+	vmmc-supply = <&reg_usdhc2_vmmc>;
+	status = "okay";
+};
+
+&usdhc3 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc3>;
+	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+	bus-width = <8>;
+	non-removable;
+	status = "okay";
+};
+
+&wdog1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_wdog>;
+	fsl,ext-reset-output;
+	status = "okay";
+};
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index b0932f1647..eb4a73b3e2 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -34,9 +34,16 @@  config TARGET_IMX8MM_EVK
 	select SUPPORT_SPL
 	select IMX8M_LPDDR4
 
+config TARGET_IMX8MN_EVK
+	bool "imx8mn DDR4 EVK board"
+	select IMX8MN
+	select SUPPORT_SPL
+	select IMX8M_DDR4
+
 endchoice
 
 source "board/freescale/imx8mq_evk/Kconfig"
 source "board/freescale/imx8mm_evk/Kconfig"
+source "board/freescale/imx8mn_evk/Kconfig"
 
 endif
diff --git a/board/freescale/imx8mn_evk/Kconfig b/board/freescale/imx8mn_evk/Kconfig
new file mode 100644
index 0000000000..38ac846802
--- /dev/null
+++ b/board/freescale/imx8mn_evk/Kconfig
@@ -0,0 +1,14 @@ 
+if TARGET_IMX8MN_EVK
+
+config SYS_BOARD
+	default "imx8mn_evk"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "imx8mn_evk"
+
+source "board/freescale/common/Kconfig"
+
+endif
diff --git a/board/freescale/imx8mn_evk/MAINTAINERS b/board/freescale/imx8mn_evk/MAINTAINERS
new file mode 100644
index 0000000000..3b0653d3c8
--- /dev/null
+++ b/board/freescale/imx8mn_evk/MAINTAINERS
@@ -0,0 +1,6 @@ 
+i.MX8MM EVK BOARD
+M:	Peng Fan <peng.fan@nxp.com>
+S:	Maintained
+F:	board/freescale/imx8mn_evk/
+F:	include/configs/imx8mn_evk.h
+F:	configs/imx8mn_ddr4_evk_defconfig
diff --git a/board/freescale/imx8mn_evk/Makefile b/board/freescale/imx8mn_evk/Makefile
new file mode 100644
index 0000000000..9511a70c31
--- /dev/null
+++ b/board/freescale/imx8mn_evk/Makefile
@@ -0,0 +1,12 @@ 
+#
+# Copyright 2018 NXP
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-y += imx8mn_evk.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-$(CONFIG_IMX8M_DDR4) += ddr4_timing.o
+endif
diff --git a/board/freescale/imx8mn_evk/ddr4_timing.c b/board/freescale/imx8mn_evk/ddr4_timing.c
new file mode 100644
index 0000000000..d83ea443af
--- /dev/null
+++ b/board/freescale/imx8mn_evk/ddr4_timing.c
@@ -0,0 +1,1213 @@ 
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ *
+ * Generated code from MX8M_DDR_tool
+ * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga
+ */
+
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+
+struct dram_cfg_param ddr_ddrc_cfg[] = {
+	{0x3d400000, 0x81040010},
+	{0x3d400030, 0x00000020},
+	{0x3d400034, 0x00221306},
+	{0x3d400050, 0x00210070},
+	{0x3d400054, 0x00010008},
+	{0x3d400060, 0x00000000},
+	{0x3d400064, 0x0092014a},
+	{0x3d4000c0, 0x00000000},
+	{0x3d4000c4, 0x00001000},
+	{0x3d4000d0, 0xc0030126},
+	{0x3d4000d4, 0x00770000},
+	{0x3d4000dc, 0x08340105},
+	{0x3d4000e0, 0x00180200},
+	{0x3d4000e4, 0x00110000},
+	{0x3d4000e8, 0x02000740},
+	{0x3d4000ec, 0x00000850},
+	{0x3d4000f4, 0x00000ec7},
+	{0x3d400100, 0x11122914},
+	{0x3d400104, 0x0004051c},
+	{0x3d400108, 0x0608050d},
+	{0x3d40010c, 0x0000400c},
+	{0x3d400110, 0x08030409},
+	{0x3d400114, 0x06060403},
+	{0x3d40011c, 0x00000606},
+	{0x3d400120, 0x07070d0c},
+	{0x3d400124, 0x0002040a},
+	{0x3d40012c, 0x1809010e},
+	{0x3d400130, 0x00000008},
+	{0x3d40013c, 0x00000000},
+	{0x3d400180, 0x01000040},
+	{0x3d400184, 0x0000493e},
+	{0x3d400190, 0x038b8207},
+	{0x3d400194, 0x02020303},
+	{0x3d400198, 0x07f04011},
+	{0x3d40019c, 0x000000b0},
+	{0x3d4001a0, 0xe0400018},
+	{0x3d4001a4, 0x0048005a},
+	{0x3d4001a8, 0x80000000},
+	{0x3d4001b0, 0x00000001},
+	{0x3d4001b4, 0x00000b07},
+	{0x3d4001b8, 0x00000004},
+	{0x3d4001c0, 0x00000001},
+	{0x3d4001c4, 0x00000000},
+	{0x3d400240, 0x06000610},
+	{0x3d400244, 0x00001323},
+	{0x3d400200, 0x00003f1f},
+	{0x3d400204, 0x003f0909},
+	{0x3d400208, 0x01010100},
+	{0x3d40020c, 0x01010101},
+	{0x3d400210, 0x00001f1f},
+	{0x3d400214, 0x07070707},
+	{0x3d400218, 0x07070707},
+	{0x3d40021c, 0x00000f07},
+	{0x3d400220, 0x00003f01},
+	{0x3d402050, 0x00210070},
+	{0x3d402064, 0x00180037},
+	{0x3d4020dc, 0x00000105},
+	{0x3d4020e0, 0x00000000},
+	{0x3d4020e8, 0x02000740},
+	{0x3d4020ec, 0x00000050},
+	{0x3d402100, 0x08030604},
+	{0x3d402104, 0x00020205},
+	{0x3d402108, 0x05050309},
+	{0x3d40210c, 0x0000400c},
+	{0x3d402110, 0x02030202},
+	{0x3d402114, 0x03030202},
+	{0x3d402118, 0x0a070008},
+	{0x3d40211c, 0x00000d09},
+	{0x3d402120, 0x08084b09},
+	{0x3d402124, 0x00020308},
+	{0x3d402128, 0x000f0d06},
+	{0x3d40212c, 0x12060111},
+	{0x3d402130, 0x00000008},
+	{0x3d40213c, 0x00000000},
+	{0x3d402180, 0x01000040},
+	{0x3d402190, 0x03848204},
+	{0x3d402194, 0x02020303},
+	{0x3d4021b4, 0x00000404},
+	{0x3d4021b8, 0x00000004},
+	{0x3d402240, 0x07000600},
+	{0x3d403050, 0x00210070},
+	{0x3d403064, 0x0006000d},
+	{0x3d4030dc, 0x00000105},
+	{0x3d4030e0, 0x00000000},
+	{0x3d4030e8, 0x02000740},
+	{0x3d4030ec, 0x00000050},
+	{0x3d403100, 0x07010101},
+	{0x3d403104, 0x00020202},
+	{0x3d403108, 0x05050309},
+	{0x3d40310c, 0x0000400c},
+	{0x3d403110, 0x01030201},
+	{0x3d403114, 0x03030202},
+	{0x3d40311c, 0x00000303},
+	{0x3d403120, 0x02020d02},
+	{0x3d403124, 0x00020208},
+	{0x3d403128, 0x000f0d06},
+	{0x3d40312c, 0x0e02010e},
+	{0x3d403130, 0x00000008},
+	{0x3d40313c, 0x00000000},
+	{0x3d403180, 0x01000040},
+	{0x3d403190, 0x03848204},
+	{0x3d403194, 0x02020303},
+	{0x3d4031b4, 0x00000404},
+	{0x3d4031b8, 0x00000004},
+	{0x3d403240, 0x07000600},
+
+	/* performance setting */
+	{ 0x3d400250, 0x00001f05 },
+	{ 0x3d400254, 0x1f },
+	{ 0x3d400264, 0x900003ff },
+	{ 0x3d40026c, 0x200003ff },
+	{ 0x3d400494, 0x01000e00 },
+	{ 0x3d400498, 0x03ff0000 },
+	{ 0x3d40049c, 0x01000e00 },
+	{ 0x3d4004a0, 0x03ff0000 },
+};
+
+/* PHY Initialize Configuration */
+struct dram_cfg_param ddr_ddrphy_cfg[] = {
+	{0x0001005f, 0x000002fd},
+	{0x0001015f, 0x000002fd},
+	{0x0001105f, 0x000002fd},
+	{0x0001115f, 0x000002fd},
+	{0x0011005f, 0x000002fd},
+	{0x0011015f, 0x000002fd},
+	{0x0011105f, 0x000002fd},
+	{0x0011115f, 0x000002fd},
+	{0x0021005f, 0x000002fd},
+	{0x0021015f, 0x000002fd},
+	{0x0021105f, 0x000002fd},
+	{0x0021115f, 0x000002fd},
+	{0x00000055, 0x00000355},
+	{0x00001055, 0x00000355},
+	{0x00002055, 0x00000355},
+	{0x00003055, 0x00000355},
+	{0x00004055, 0x00000055},
+	{0x00005055, 0x00000055},
+	{0x00006055, 0x00000355},
+	{0x00007055, 0x00000355},
+	{0x00008055, 0x00000355},
+	{0x00009055, 0x00000355},
+	{0x000200c5, 0x0000000a},
+	{0x001200c5, 0x00000007},
+	{0x002200c5, 0x00000007},
+	{0x0002002e, 0x00000002},
+	{0x0012002e, 0x00000002},
+	{0x0022002e, 0x00000002},
+	{0x00020024, 0x00000008},
+	{0x0002003a, 0x00000002},
+	{0x0002007d, 0x00000212},
+	{0x0002007c, 0x00000061},
+	{0x00120024, 0x00000008},
+	{0x0002003a, 0x00000002},
+	{0x0012007d, 0x00000212},
+	{0x0012007c, 0x00000061},
+	{0x00220024, 0x00000008},
+	{0x0002003a, 0x00000002},
+	{0x0022007d, 0x00000212},
+	{0x0022007c, 0x00000061},
+	{0x00020056, 0x00000006},
+	{0x00120056, 0x0000000a},
+	{0x00220056, 0x0000000a},
+	{0x0001004d, 0x0000001a},
+	{0x0001014d, 0x0000001a},
+	{0x0001104d, 0x0000001a},
+	{0x0001114d, 0x0000001a},
+	{0x0011004d, 0x0000001a},
+	{0x0011014d, 0x0000001a},
+	{0x0011104d, 0x0000001a},
+	{0x0011114d, 0x0000001a},
+	{0x0021004d, 0x0000001a},
+	{0x0021014d, 0x0000001a},
+	{0x0021104d, 0x0000001a},
+	{0x0021114d, 0x0000001a},
+	{0x00010049, 0x00000e38},
+	{0x00010149, 0x00000e38},
+	{0x00011049, 0x00000e38},
+	{0x00011149, 0x00000e38},
+	{0x00110049, 0x00000e38},
+	{0x00110149, 0x00000e38},
+	{0x00111049, 0x00000e38},
+	{0x00111149, 0x00000e38},
+	{0x00210049, 0x00000e38},
+	{0x00210149, 0x00000e38},
+	{0x00211049, 0x00000e38},
+	{0x00211149, 0x00000e38},
+	{0x00000043, 0x00000063},
+	{0x00001043, 0x00000063},
+	{0x00002043, 0x00000063},
+	{0x00003043, 0x00000063},
+	{0x00004043, 0x00000063},
+	{0x00005043, 0x00000063},
+	{0x00006043, 0x00000063},
+	{0x00007043, 0x00000063},
+	{0x00008043, 0x00000063},
+	{0x00009043, 0x00000063},
+	{0x00020018, 0x00000001},
+	{0x00020075, 0x00000002},
+	{0x00020050, 0x00000000},
+	{0x00020008, 0x00000258},
+	{0x00120008, 0x00000064},
+	{0x00220008, 0x00000019},
+	{0x00020088, 0x00000009},
+	{0x000200b2, 0x00000268},
+	{0x00010043, 0x000005b1},
+	{0x00010143, 0x000005b1},
+	{0x00011043, 0x000005b1},
+	{0x00011143, 0x000005b1},
+	{0x001200b2, 0x00000268},
+	{0x00110043, 0x000005b1},
+	{0x00110143, 0x000005b1},
+	{0x00111043, 0x000005b1},
+	{0x00111143, 0x000005b1},
+	{0x002200b2, 0x00000268},
+	{0x00210043, 0x000005b1},
+	{0x00210143, 0x000005b1},
+	{0x00211043, 0x000005b1},
+	{0x00211143, 0x000005b1},
+	{0x0002005b, 0x00007529},
+	{0x0002005c, 0x00000000},
+	{0x000200fa, 0x00000001},
+	{0x001200fa, 0x00000001},
+	{0x002200fa, 0x00000001},
+	{0x00020019, 0x00000005},
+	{0x00120019, 0x00000005},
+	{0x00220019, 0x00000005},
+	{0x000200f0, 0x00005665},
+	{0x000200f1, 0x00005555},
+	{0x000200f2, 0x00005555},
+	{0x000200f3, 0x00005555},
+	{0x000200f4, 0x00005555},
+	{0x000200f5, 0x00005555},
+	{0x000200f6, 0x00005555},
+	{0x000200f7, 0x0000f000},
+	{0x0001004a, 0x00000500},
+	{0x0001104a, 0x00000500},
+	{0x00020025, 0x00000000},
+	{0x0002002d, 0x00000000},
+	{0x0012002d, 0x00000000},
+	{0x0022002d, 0x00000000},
+	{0x0002002c, 0x00000000},
+	{0x000200c7, 0x00000021},
+	{0x000200ca, 0x00000024},
+	{0x000200cc, 0x000001f7},
+	{0x001200c7, 0x00000021},
+	{0x001200ca, 0x00000024},
+	{0x001200cc, 0x000001f7},
+	{0x002200c7, 0x00000021},
+	{0x002200ca, 0x00000024},
+	{0x002200cc, 0x000001f7},
+};
+
+/* ddr phy trained csr */
+struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+	{0x0200b2, 0x0},
+	{0x1200b2, 0x0},
+	{0x2200b2, 0x0},
+	{0x0200cb, 0x0},
+	{0x010043, 0x0},
+	{0x110043, 0x0},
+	{0x210043, 0x0},
+	{0x010143, 0x0},
+	{0x110143, 0x0},
+	{0x210143, 0x0},
+	{0x011043, 0x0},
+	{0x111043, 0x0},
+	{0x211043, 0x0},
+	{0x011143, 0x0},
+	{0x111143, 0x0},
+	{0x211143, 0x0},
+	{0x000080, 0x0},
+	{0x100080, 0x0},
+	{0x200080, 0x0},
+	{0x001080, 0x0},
+	{0x101080, 0x0},
+	{0x201080, 0x0},
+	{0x002080, 0x0},
+	{0x102080, 0x0},
+	{0x202080, 0x0},
+	{0x003080, 0x0},
+	{0x103080, 0x0},
+	{0x203080, 0x0},
+	{0x004080, 0x0},
+	{0x104080, 0x0},
+	{0x204080, 0x0},
+	{0x005080, 0x0},
+	{0x105080, 0x0},
+	{0x205080, 0x0},
+	{0x006080, 0x0},
+	{0x106080, 0x0},
+	{0x206080, 0x0},
+	{0x007080, 0x0},
+	{0x107080, 0x0},
+	{0x207080, 0x0},
+	{0x008080, 0x0},
+	{0x108080, 0x0},
+	{0x208080, 0x0},
+	{0x009080, 0x0},
+	{0x109080, 0x0},
+	{0x209080, 0x0},
+	{0x010080, 0x0},
+	{0x110080, 0x0},
+	{0x210080, 0x0},
+	{0x010180, 0x0},
+	{0x110180, 0x0},
+	{0x210180, 0x0},
+	{0x010081, 0x0},
+	{0x110081, 0x0},
+	{0x210081, 0x0},
+	{0x010181, 0x0},
+	{0x110181, 0x0},
+	{0x210181, 0x0},
+	{0x010082, 0x0},
+	{0x110082, 0x0},
+	{0x210082, 0x0},
+	{0x010182, 0x0},
+	{0x110182, 0x0},
+	{0x210182, 0x0},
+	{0x010083, 0x0},
+	{0x110083, 0x0},
+	{0x210083, 0x0},
+	{0x010183, 0x0},
+	{0x110183, 0x0},
+	{0x210183, 0x0},
+	{0x011080, 0x0},
+	{0x111080, 0x0},
+	{0x211080, 0x0},
+	{0x011180, 0x0},
+	{0x111180, 0x0},
+	{0x211180, 0x0},
+	{0x011081, 0x0},
+	{0x111081, 0x0},
+	{0x211081, 0x0},
+	{0x011181, 0x0},
+	{0x111181, 0x0},
+	{0x211181, 0x0},
+	{0x011082, 0x0},
+	{0x111082, 0x0},
+	{0x211082, 0x0},
+	{0x011182, 0x0},
+	{0x111182, 0x0},
+	{0x211182, 0x0},
+	{0x011083, 0x0},
+	{0x111083, 0x0},
+	{0x211083, 0x0},
+	{0x011183, 0x0},
+	{0x111183, 0x0},
+	{0x211183, 0x0},
+	{0x0100d0, 0x0},
+	{0x1100d0, 0x0},
+	{0x2100d0, 0x0},
+	{0x0101d0, 0x0},
+	{0x1101d0, 0x0},
+	{0x2101d0, 0x0},
+	{0x0100d1, 0x0},
+	{0x1100d1, 0x0},
+	{0x2100d1, 0x0},
+	{0x0101d1, 0x0},
+	{0x1101d1, 0x0},
+	{0x2101d1, 0x0},
+	{0x0100d2, 0x0},
+	{0x1100d2, 0x0},
+	{0x2100d2, 0x0},
+	{0x0101d2, 0x0},
+	{0x1101d2, 0x0},
+	{0x2101d2, 0x0},
+	{0x0100d3, 0x0},
+	{0x1100d3, 0x0},
+	{0x2100d3, 0x0},
+	{0x0101d3, 0x0},
+	{0x1101d3, 0x0},
+	{0x2101d3, 0x0},
+	{0x0110d0, 0x0},
+	{0x1110d0, 0x0},
+	{0x2110d0, 0x0},
+	{0x0111d0, 0x0},
+	{0x1111d0, 0x0},
+	{0x2111d0, 0x0},
+	{0x0110d1, 0x0},
+	{0x1110d1, 0x0},
+	{0x2110d1, 0x0},
+	{0x0111d1, 0x0},
+	{0x1111d1, 0x0},
+	{0x2111d1, 0x0},
+	{0x0110d2, 0x0},
+	{0x1110d2, 0x0},
+	{0x2110d2, 0x0},
+	{0x0111d2, 0x0},
+	{0x1111d2, 0x0},
+	{0x2111d2, 0x0},
+	{0x0110d3, 0x0},
+	{0x1110d3, 0x0},
+	{0x2110d3, 0x0},
+	{0x0111d3, 0x0},
+	{0x1111d3, 0x0},
+	{0x2111d3, 0x0},
+	{0x010068, 0x0},
+	{0x010168, 0x0},
+	{0x010268, 0x0},
+	{0x010368, 0x0},
+	{0x010468, 0x0},
+	{0x010568, 0x0},
+	{0x010668, 0x0},
+	{0x010768, 0x0},
+	{0x010868, 0x0},
+	{0x010069, 0x0},
+	{0x010169, 0x0},
+	{0x010269, 0x0},
+	{0x010369, 0x0},
+	{0x010469, 0x0},
+	{0x010569, 0x0},
+	{0x010669, 0x0},
+	{0x010769, 0x0},
+	{0x010869, 0x0},
+	{0x01006a, 0x0},
+	{0x01016a, 0x0},
+	{0x01026a, 0x0},
+	{0x01036a, 0x0},
+	{0x01046a, 0x0},
+	{0x01056a, 0x0},
+	{0x01066a, 0x0},
+	{0x01076a, 0x0},
+	{0x01086a, 0x0},
+	{0x01006b, 0x0},
+	{0x01016b, 0x0},
+	{0x01026b, 0x0},
+	{0x01036b, 0x0},
+	{0x01046b, 0x0},
+	{0x01056b, 0x0},
+	{0x01066b, 0x0},
+	{0x01076b, 0x0},
+	{0x01086b, 0x0},
+	{0x011068, 0x0},
+	{0x011168, 0x0},
+	{0x011268, 0x0},
+	{0x011368, 0x0},
+	{0x011468, 0x0},
+	{0x011568, 0x0},
+	{0x011668, 0x0},
+	{0x011768, 0x0},
+	{0x011868, 0x0},
+	{0x011069, 0x0},
+	{0x011169, 0x0},
+	{0x011269, 0x0},
+	{0x011369, 0x0},
+	{0x011469, 0x0},
+	{0x011569, 0x0},
+	{0x011669, 0x0},
+	{0x011769, 0x0},
+	{0x011869, 0x0},
+	{0x01106a, 0x0},
+	{0x01116a, 0x0},
+	{0x01126a, 0x0},
+	{0x01136a, 0x0},
+	{0x01146a, 0x0},
+	{0x01156a, 0x0},
+	{0x01166a, 0x0},
+	{0x01176a, 0x0},
+	{0x01186a, 0x0},
+	{0x01106b, 0x0},
+	{0x01116b, 0x0},
+	{0x01126b, 0x0},
+	{0x01136b, 0x0},
+	{0x01146b, 0x0},
+	{0x01156b, 0x0},
+	{0x01166b, 0x0},
+	{0x01176b, 0x0},
+	{0x01186b, 0x0},
+	{0x01008c, 0x0},
+	{0x11008c, 0x0},
+	{0x21008c, 0x0},
+	{0x01018c, 0x0},
+	{0x11018c, 0x0},
+	{0x21018c, 0x0},
+	{0x01008d, 0x0},
+	{0x11008d, 0x0},
+	{0x21008d, 0x0},
+	{0x01018d, 0x0},
+	{0x11018d, 0x0},
+	{0x21018d, 0x0},
+	{0x01008e, 0x0},
+	{0x11008e, 0x0},
+	{0x21008e, 0x0},
+	{0x01018e, 0x0},
+	{0x11018e, 0x0},
+	{0x21018e, 0x0},
+	{0x01008f, 0x0},
+	{0x11008f, 0x0},
+	{0x21008f, 0x0},
+	{0x01018f, 0x0},
+	{0x11018f, 0x0},
+	{0x21018f, 0x0},
+	{0x01108c, 0x0},
+	{0x11108c, 0x0},
+	{0x21108c, 0x0},
+	{0x01118c, 0x0},
+	{0x11118c, 0x0},
+	{0x21118c, 0x0},
+	{0x01108d, 0x0},
+	{0x11108d, 0x0},
+	{0x21108d, 0x0},
+	{0x01118d, 0x0},
+	{0x11118d, 0x0},
+	{0x21118d, 0x0},
+	{0x01108e, 0x0},
+	{0x11108e, 0x0},
+	{0x21108e, 0x0},
+	{0x01118e, 0x0},
+	{0x11118e, 0x0},
+	{0x21118e, 0x0},
+	{0x01108f, 0x0},
+	{0x11108f, 0x0},
+	{0x21108f, 0x0},
+	{0x01118f, 0x0},
+	{0x11118f, 0x0},
+	{0x21118f, 0x0},
+	{0x0100c0, 0x0},
+	{0x1100c0, 0x0},
+	{0x2100c0, 0x0},
+	{0x0101c0, 0x0},
+	{0x1101c0, 0x0},
+	{0x2101c0, 0x0},
+	{0x0102c0, 0x0},
+	{0x1102c0, 0x0},
+	{0x2102c0, 0x0},
+	{0x0103c0, 0x0},
+	{0x1103c0, 0x0},
+	{0x2103c0, 0x0},
+	{0x0104c0, 0x0},
+	{0x1104c0, 0x0},
+	{0x2104c0, 0x0},
+	{0x0105c0, 0x0},
+	{0x1105c0, 0x0},
+	{0x2105c0, 0x0},
+	{0x0106c0, 0x0},
+	{0x1106c0, 0x0},
+	{0x2106c0, 0x0},
+	{0x0107c0, 0x0},
+	{0x1107c0, 0x0},
+	{0x2107c0, 0x0},
+	{0x0108c0, 0x0},
+	{0x1108c0, 0x0},
+	{0x2108c0, 0x0},
+	{0x0100c1, 0x0},
+	{0x1100c1, 0x0},
+	{0x2100c1, 0x0},
+	{0x0101c1, 0x0},
+	{0x1101c1, 0x0},
+	{0x2101c1, 0x0},
+	{0x0102c1, 0x0},
+	{0x1102c1, 0x0},
+	{0x2102c1, 0x0},
+	{0x0103c1, 0x0},
+	{0x1103c1, 0x0},
+	{0x2103c1, 0x0},
+	{0x0104c1, 0x0},
+	{0x1104c1, 0x0},
+	{0x2104c1, 0x0},
+	{0x0105c1, 0x0},
+	{0x1105c1, 0x0},
+	{0x2105c1, 0x0},
+	{0x0106c1, 0x0},
+	{0x1106c1, 0x0},
+	{0x2106c1, 0x0},
+	{0x0107c1, 0x0},
+	{0x1107c1, 0x0},
+	{0x2107c1, 0x0},
+	{0x0108c1, 0x0},
+	{0x1108c1, 0x0},
+	{0x2108c1, 0x0},
+	{0x0100c2, 0x0},
+	{0x1100c2, 0x0},
+	{0x2100c2, 0x0},
+	{0x0101c2, 0x0},
+	{0x1101c2, 0x0},
+	{0x2101c2, 0x0},
+	{0x0102c2, 0x0},
+	{0x1102c2, 0x0},
+	{0x2102c2, 0x0},
+	{0x0103c2, 0x0},
+	{0x1103c2, 0x0},
+	{0x2103c2, 0x0},
+	{0x0104c2, 0x0},
+	{0x1104c2, 0x0},
+	{0x2104c2, 0x0},
+	{0x0105c2, 0x0},
+	{0x1105c2, 0x0},
+	{0x2105c2, 0x0},
+	{0x0106c2, 0x0},
+	{0x1106c2, 0x0},
+	{0x2106c2, 0x0},
+	{0x0107c2, 0x0},
+	{0x1107c2, 0x0},
+	{0x2107c2, 0x0},
+	{0x0108c2, 0x0},
+	{0x1108c2, 0x0},
+	{0x2108c2, 0x0},
+	{0x0100c3, 0x0},
+	{0x1100c3, 0x0},
+	{0x2100c3, 0x0},
+	{0x0101c3, 0x0},
+	{0x1101c3, 0x0},
+	{0x2101c3, 0x0},
+	{0x0102c3, 0x0},
+	{0x1102c3, 0x0},
+	{0x2102c3, 0x0},
+	{0x0103c3, 0x0},
+	{0x1103c3, 0x0},
+	{0x2103c3, 0x0},
+	{0x0104c3, 0x0},
+	{0x1104c3, 0x0},
+	{0x2104c3, 0x0},
+	{0x0105c3, 0x0},
+	{0x1105c3, 0x0},
+	{0x2105c3, 0x0},
+	{0x0106c3, 0x0},
+	{0x1106c3, 0x0},
+	{0x2106c3, 0x0},
+	{0x0107c3, 0x0},
+	{0x1107c3, 0x0},
+	{0x2107c3, 0x0},
+	{0x0108c3, 0x0},
+	{0x1108c3, 0x0},
+	{0x2108c3, 0x0},
+	{0x0110c0, 0x0},
+	{0x1110c0, 0x0},
+	{0x2110c0, 0x0},
+	{0x0111c0, 0x0},
+	{0x1111c0, 0x0},
+	{0x2111c0, 0x0},
+	{0x0112c0, 0x0},
+	{0x1112c0, 0x0},
+	{0x2112c0, 0x0},
+	{0x0113c0, 0x0},
+	{0x1113c0, 0x0},
+	{0x2113c0, 0x0},
+	{0x0114c0, 0x0},
+	{0x1114c0, 0x0},
+	{0x2114c0, 0x0},
+	{0x0115c0, 0x0},
+	{0x1115c0, 0x0},
+	{0x2115c0, 0x0},
+	{0x0116c0, 0x0},
+	{0x1116c0, 0x0},
+	{0x2116c0, 0x0},
+	{0x0117c0, 0x0},
+	{0x1117c0, 0x0},
+	{0x2117c0, 0x0},
+	{0x0118c0, 0x0},
+	{0x1118c0, 0x0},
+	{0x2118c0, 0x0},
+	{0x0110c1, 0x0},
+	{0x1110c1, 0x0},
+	{0x2110c1, 0x0},
+	{0x0111c1, 0x0},
+	{0x1111c1, 0x0},
+	{0x2111c1, 0x0},
+	{0x0112c1, 0x0},
+	{0x1112c1, 0x0},
+	{0x2112c1, 0x0},
+	{0x0113c1, 0x0},
+	{0x1113c1, 0x0},
+	{0x2113c1, 0x0},
+	{0x0114c1, 0x0},
+	{0x1114c1, 0x0},
+	{0x2114c1, 0x0},
+	{0x0115c1, 0x0},
+	{0x1115c1, 0x0},
+	{0x2115c1, 0x0},
+	{0x0116c1, 0x0},
+	{0x1116c1, 0x0},
+	{0x2116c1, 0x0},
+	{0x0117c1, 0x0},
+	{0x1117c1, 0x0},
+	{0x2117c1, 0x0},
+	{0x0118c1, 0x0},
+	{0x1118c1, 0x0},
+	{0x2118c1, 0x0},
+	{0x0110c2, 0x0},
+	{0x1110c2, 0x0},
+	{0x2110c2, 0x0},
+	{0x0111c2, 0x0},
+	{0x1111c2, 0x0},
+	{0x2111c2, 0x0},
+	{0x0112c2, 0x0},
+	{0x1112c2, 0x0},
+	{0x2112c2, 0x0},
+	{0x0113c2, 0x0},
+	{0x1113c2, 0x0},
+	{0x2113c2, 0x0},
+	{0x0114c2, 0x0},
+	{0x1114c2, 0x0},
+	{0x2114c2, 0x0},
+	{0x0115c2, 0x0},
+	{0x1115c2, 0x0},
+	{0x2115c2, 0x0},
+	{0x0116c2, 0x0},
+	{0x1116c2, 0x0},
+	{0x2116c2, 0x0},
+	{0x0117c2, 0x0},
+	{0x1117c2, 0x0},
+	{0x2117c2, 0x0},
+	{0x0118c2, 0x0},
+	{0x1118c2, 0x0},
+	{0x2118c2, 0x0},
+	{0x0110c3, 0x0},
+	{0x1110c3, 0x0},
+	{0x2110c3, 0x0},
+	{0x0111c3, 0x0},
+	{0x1111c3, 0x0},
+	{0x2111c3, 0x0},
+	{0x0112c3, 0x0},
+	{0x1112c3, 0x0},
+	{0x2112c3, 0x0},
+	{0x0113c3, 0x0},
+	{0x1113c3, 0x0},
+	{0x2113c3, 0x0},
+	{0x0114c3, 0x0},
+	{0x1114c3, 0x0},
+	{0x2114c3, 0x0},
+	{0x0115c3, 0x0},
+	{0x1115c3, 0x0},
+	{0x2115c3, 0x0},
+	{0x0116c3, 0x0},
+	{0x1116c3, 0x0},
+	{0x2116c3, 0x0},
+	{0x0117c3, 0x0},
+	{0x1117c3, 0x0},
+	{0x2117c3, 0x0},
+	{0x0118c3, 0x0},
+	{0x1118c3, 0x0},
+	{0x2118c3, 0x0},
+	{0x010020, 0x0},
+	{0x110020, 0x0},
+	{0x210020, 0x0},
+	{0x011020, 0x0},
+	{0x111020, 0x0},
+	{0x211020, 0x0},
+	{0x02007d, 0x0},
+	{0x12007d, 0x0},
+	{0x22007d, 0x0},
+	{0x010040, 0x0},
+	{0x010140, 0x0},
+	{0x010240, 0x0},
+	{0x010340, 0x0},
+	{0x010440, 0x0},
+	{0x010540, 0x0},
+	{0x010640, 0x0},
+	{0x010740, 0x0},
+	{0x010840, 0x0},
+	{0x010030, 0x0},
+	{0x010130, 0x0},
+	{0x010230, 0x0},
+	{0x010330, 0x0},
+	{0x010430, 0x0},
+	{0x010530, 0x0},
+	{0x010630, 0x0},
+	{0x010730, 0x0},
+	{0x010830, 0x0},
+	{0x011040, 0x0},
+	{0x011140, 0x0},
+	{0x011240, 0x0},
+	{0x011340, 0x0},
+	{0x011440, 0x0},
+	{0x011540, 0x0},
+	{0x011640, 0x0},
+	{0x011740, 0x0},
+	{0x011840, 0x0},
+	{0x011030, 0x0},
+	{0x011130, 0x0},
+	{0x011230, 0x0},
+	{0x011330, 0x0},
+	{0x011430, 0x0},
+	{0x011530, 0x0},
+	{0x011630, 0x0},
+	{0x011730, 0x0},
+	{0x011830, 0x0},
+};
+
+/* P0 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_cfg[] = {
+	{0x000d0000, 0x00000000},
+	{0x00020060, 0x00000002},
+	{0x00054000, 0x00000000},
+	{0x00054001, 0x00000000},
+	{0x00054002, 0x00000000},
+	{0x00054003, 0x00000960},
+	{0x00054004, 0x00000002},
+	{0x00054005, 0x00000000},
+	{0x00054006, 0x0000025e},
+	{0x00054007, 0x00001000},
+	{0x00054008, 0x00000101},
+	{0x00054009, 0x00000000},
+	{0x0005400a, 0x00000000},
+	{0x0005400b, 0x0000031f},
+	{0x0005400c, 0x000000c8},
+	{0x0005400d, 0x00000100},
+	{0x0005400e, 0x00000000},
+	{0x0005400f, 0x00000000},
+	{0x00054010, 0x00000000},
+	{0x00054011, 0x00000000},
+	{0x00054012, 0x00000001},
+	{0x0005402f, 0x00000834},
+	{0x00054030, 0x00000105},
+	{0x00054031, 0x00000018},
+	{0x00054032, 0x00000200},
+	{0x00054033, 0x00000200},
+	{0x00054034, 0x00000740},
+	{0x00054035, 0x00000850},
+	{0x00054036, 0x00000103},
+	{0x00054037, 0x00000000},
+	{0x00054038, 0x00000000},
+	{0x00054039, 0x00000000},
+	{0x0005403a, 0x00000000},
+	{0x0005403b, 0x00000000},
+	{0x0005403c, 0x00000000},
+	{0x0005403d, 0x00000000},
+	{0x0005403e, 0x00000000},
+	{0x0005403f, 0x00001221},
+	{0x000541fc, 0x00000100},
+	{0x000d0000, 0x00000001},
+};
+
+/* P1 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp1_cfg[] = {
+	{0x000d0000, 0x00000000},
+	{0x00054000, 0x00000000},
+	{0x00054001, 0x00000000},
+	{0x00054002, 0x00000101},
+	{0x00054003, 0x00000190},
+	{0x00054004, 0x00000002},
+	{0x00054005, 0x00000000},
+	{0x00054006, 0x0000025e},
+	{0x00054007, 0x00001000},
+	{0x00054008, 0x00000101},
+	{0x00054009, 0x00000000},
+	{0x0005400a, 0x00000000},
+	{0x0005400b, 0x0000021f},
+	{0x0005400c, 0x000000c8},
+	{0x0005400d, 0x00000100},
+	{0x0005400e, 0x00000000},
+	{0x0005400f, 0x00000000},
+	{0x00054010, 0x00000000},
+	{0x00054011, 0x00000000},
+	{0x00054012, 0x00000001},
+	{0x0005402f, 0x00000000},
+	{0x00054030, 0x00000105},
+	{0x00054031, 0x00000000},
+	{0x00054032, 0x00000000},
+	{0x00054033, 0x00000200},
+	{0x00054034, 0x00000740},
+	{0x00054035, 0x00000050},
+	{0x00054036, 0x00000103},
+	{0x00054037, 0x00000000},
+	{0x00054038, 0x00000000},
+	{0x00054039, 0x00000000},
+	{0x0005403a, 0x00000000},
+	{0x0005403b, 0x00000000},
+	{0x0005403c, 0x00000000},
+	{0x0005403d, 0x00000000},
+	{0x0005403e, 0x00000000},
+	{0x0005403f, 0x00001221},
+	{0x000541fc, 0x00000100},
+	{0x000d0000, 0x00000001},
+};
+
+/* P2 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp2_cfg[] = {
+	{0x000d0000, 0x00000000},
+	{0x00054000, 0x00000000},
+	{0x00054001, 0x00000000},
+	{0x00054002, 0x00000102},
+	{0x00054003, 0x00000064},
+	{0x00054004, 0x00000002},
+	{0x00054005, 0x00000000},
+	{0x00054006, 0x0000025e},
+	{0x00054007, 0x00001000},
+	{0x00054008, 0x00000101},
+	{0x00054009, 0x00000000},
+	{0x0005400a, 0x00000000},
+	{0x0005400b, 0x0000021f},
+	{0x0005400c, 0x000000c8},
+	{0x0005400d, 0x00000100},
+	{0x0005400e, 0x00000000},
+	{0x0005400f, 0x00000000},
+	{0x00054010, 0x00000000},
+	{0x00054011, 0x00000000},
+	{0x00054012, 0x00000001},
+	{0x0005402f, 0x00000000},
+	{0x00054030, 0x00000105},
+	{0x00054031, 0x00000000},
+	{0x00054032, 0x00000000},
+	{0x00054033, 0x00000200},
+	{0x00054034, 0x00000740},
+	{0x00054035, 0x00000050},
+	{0x00054036, 0x00000103},
+	{0x00054037, 0x00000000},
+	{0x00054038, 0x00000000},
+	{0x00054039, 0x00000000},
+	{0x0005403a, 0x00000000},
+	{0x0005403b, 0x00000000},
+	{0x0005403c, 0x00000000},
+	{0x0005403d, 0x00000000},
+	{0x0005403e, 0x00000000},
+	{0x0005403f, 0x00001221},
+	{0x000541fc, 0x00000100},
+	{0x000d0000, 0x00000001},
+};
+
+/* P0 2D message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+	{0x000d0000, 0x00000000},
+	{0x00054000, 0x00000000},
+	{0x00054001, 0x00000000},
+	{0x00054002, 0x00000000},
+	{0x00054003, 0x00000960},
+	{0x00054004, 0x00000002},
+	{0x00054005, 0x00000000},
+	{0x00054006, 0x0000025e},
+	{0x00054007, 0x00001000},
+	{0x00054008, 0x00000101},
+	{0x00054009, 0x00000000},
+	{0x0005400a, 0x00000000},
+	{0x0005400b, 0x00000061},
+	{0x0005400c, 0x000000c8},
+	{0x0005400d, 0x00000100},
+	{0x0005400e, 0x00001f7f},
+	{0x0005400f, 0x00000000},
+	{0x00054010, 0x00000000},
+	{0x00054011, 0x00000000},
+	{0x00054012, 0x00000001},
+	{0x0005402f, 0x00000834},
+	{0x00054030, 0x00000105},
+	{0x00054031, 0x00000018},
+	{0x00054032, 0x00000200},
+	{0x00054033, 0x00000200},
+	{0x00054034, 0x00000740},
+	{0x00054035, 0x00000850},
+	{0x00054036, 0x00000103},
+	{0x00054037, 0x00000000},
+	{0x00054038, 0x00000000},
+	{0x00054039, 0x00000000},
+	{0x0005403a, 0x00000000},
+	{0x0005403b, 0x00000000},
+	{0x0005403c, 0x00000000},
+	{0x0005403d, 0x00000000},
+	{0x0005403e, 0x00000000},
+	{0x0005403f, 0x00001221},
+	{0x000541fc, 0x00000100},
+	{0x000d0000, 0x00000001},
+};
+
+/* DRAM PHY init engine image */
+struct dram_cfg_param ddr_phy_pie[] = {
+	{0xd0000, 0x0},
+	{0x90000, 0x10},
+	{0x90001, 0x400},
+	{0x90002, 0x10e},
+	{0x90003, 0x0},
+	{0x90004, 0x0},
+	{0x90005, 0x8},
+	{0x90029, 0xb},
+	{0x9002a, 0x480},
+	{0x9002b, 0x109},
+	{0x9002c, 0x8},
+	{0x9002d, 0x448},
+	{0x9002e, 0x139},
+	{0x9002f, 0x8},
+	{0x90030, 0x478},
+	{0x90031, 0x109},
+	{0x90032, 0x2},
+	{0x90033, 0x10},
+	{0x90034, 0x139},
+	{0x90035, 0xb},
+	{0x90036, 0x7c0},
+	{0x90037, 0x139},
+	{0x90038, 0x44},
+	{0x90039, 0x633},
+	{0x9003a, 0x159},
+	{0x9003b, 0x14f},
+	{0x9003c, 0x630},
+	{0x9003d, 0x159},
+	{0x9003e, 0x47},
+	{0x9003f, 0x633},
+	{0x90040, 0x149},
+	{0x90041, 0x4f},
+	{0x90042, 0x633},
+	{0x90043, 0x179},
+	{0x90044, 0x8},
+	{0x90045, 0xe0},
+	{0x90046, 0x109},
+	{0x90047, 0x0},
+	{0x90048, 0x7c8},
+	{0x90049, 0x109},
+	{0x9004a, 0x0},
+	{0x9004b, 0x1},
+	{0x9004c, 0x8},
+	{0x9004d, 0x0},
+	{0x9004e, 0x45a},
+	{0x9004f, 0x9},
+	{0x90050, 0x0},
+	{0x90051, 0x448},
+	{0x90052, 0x109},
+	{0x90053, 0x40},
+	{0x90054, 0x633},
+	{0x90055, 0x179},
+	{0x90056, 0x1},
+	{0x90057, 0x618},
+	{0x90058, 0x109},
+	{0x90059, 0x40c0},
+	{0x9005a, 0x633},
+	{0x9005b, 0x149},
+	{0x9005c, 0x8},
+	{0x9005d, 0x4},
+	{0x9005e, 0x48},
+	{0x9005f, 0x4040},
+	{0x90060, 0x633},
+	{0x90061, 0x149},
+	{0x90062, 0x0},
+	{0x90063, 0x4},
+	{0x90064, 0x48},
+	{0x90065, 0x40},
+	{0x90066, 0x633},
+	{0x90067, 0x149},
+	{0x90068, 0x10},
+	{0x90069, 0x4},
+	{0x9006a, 0x18},
+	{0x9006b, 0x0},
+	{0x9006c, 0x4},
+	{0x9006d, 0x78},
+	{0x9006e, 0x549},
+	{0x9006f, 0x633},
+	{0x90070, 0x159},
+	{0x90071, 0xd49},
+	{0x90072, 0x633},
+	{0x90073, 0x159},
+	{0x90074, 0x94a},
+	{0x90075, 0x633},
+	{0x90076, 0x159},
+	{0x90077, 0x441},
+	{0x90078, 0x633},
+	{0x90079, 0x149},
+	{0x9007a, 0x42},
+	{0x9007b, 0x633},
+	{0x9007c, 0x149},
+	{0x9007d, 0x1},
+	{0x9007e, 0x633},
+	{0x9007f, 0x149},
+	{0x90080, 0x0},
+	{0x90081, 0xe0},
+	{0x90082, 0x109},
+	{0x90083, 0xa},
+	{0x90084, 0x10},
+	{0x90085, 0x109},
+	{0x90086, 0x9},
+	{0x90087, 0x3c0},
+	{0x90088, 0x149},
+	{0x90089, 0x9},
+	{0x9008a, 0x3c0},
+	{0x9008b, 0x159},
+	{0x9008c, 0x18},
+	{0x9008d, 0x10},
+	{0x9008e, 0x109},
+	{0x9008f, 0x0},
+	{0x90090, 0x3c0},
+	{0x90091, 0x109},
+	{0x90092, 0x18},
+	{0x90093, 0x4},
+	{0x90094, 0x48},
+	{0x90095, 0x18},
+	{0x90096, 0x4},
+	{0x90097, 0x58},
+	{0x90098, 0xb},
+	{0x90099, 0x10},
+	{0x9009a, 0x109},
+	{0x9009b, 0x1},
+	{0x9009c, 0x10},
+	{0x9009d, 0x109},
+	{0x9009e, 0x5},
+	{0x9009f, 0x7c0},
+	{0x900a0, 0x109},
+	{0x900a1, 0x0},
+	{0x900a2, 0x8140},
+	{0x900a3, 0x10c},
+	{0x900a4, 0x10},
+	{0x900a5, 0x8138},
+	{0x900a6, 0x10c},
+	{0x900a7, 0x8},
+	{0x900a8, 0x7c8},
+	{0x900a9, 0x101},
+	{0x900aa, 0x8},
+	{0x900ab, 0x448},
+	{0x900ac, 0x109},
+	{0x900ad, 0xf},
+	{0x900ae, 0x7c0},
+	{0x900af, 0x109},
+	{0x900b0, 0x47},
+	{0x900b1, 0x630},
+	{0x900b2, 0x109},
+	{0x900b3, 0x8},
+	{0x900b4, 0x618},
+	{0x900b5, 0x109},
+	{0x900b6, 0x8},
+	{0x900b7, 0xe0},
+	{0x900b8, 0x109},
+	{0x900b9, 0x0},
+	{0x900ba, 0x7c8},
+	{0x900bb, 0x109},
+	{0x900bc, 0x8},
+	{0x900bd, 0x8140},
+	{0x900be, 0x10c},
+	{0x900bf, 0x0},
+	{0x900c0, 0x1},
+	{0x900c1, 0x8},
+	{0x900c2, 0x8},
+	{0x900c3, 0x4},
+	{0x900c4, 0x8},
+	{0x900c5, 0x8},
+	{0x900c6, 0x7c8},
+	{0x900c7, 0x101},
+	{0x90006, 0x0},
+	{0x90007, 0x0},
+	{0x90008, 0x8},
+	{0x90009, 0x0},
+	{0x9000a, 0x0},
+	{0x9000b, 0x0},
+	{0xd00e7, 0x400},
+	{0x90017, 0x0},
+	{0x90026, 0x2b},
+	{0x2000b, 0x4b},
+	{0x2000c, 0x96},
+	{0x2000d, 0x5dc},
+	{0x2000e, 0x2c},
+	{0x12000b, 0xc},
+	{0x12000c, 0x16},
+	{0x12000d, 0xfa},
+	{0x12000e, 0x10},
+	{0x22000b, 0x3},
+	{0x22000c, 0x3},
+	{0x22000d, 0x3e},
+	{0x22000e, 0x10},
+	{0x9000c, 0x0},
+	{0x9000d, 0x173},
+	{0x9000e, 0x60},
+	{0x9000f, 0x6110},
+	{0x90010, 0x2152},
+	{0x90011, 0xdfbd},
+	{0x90012, 0xffff},
+	{0x90013, 0x6152},
+	{0x20089, 0x1},
+	{0x20088, 0x19},
+	{0xc0080, 0x0},
+	{0xd0000, 0x1},
+};
+
+struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+	{
+		/* P0 2400mts 1D */
+		.drate = 2400,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp0_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+	},
+	{
+		/* P1 400mts 1D */
+		.drate = 400,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp1_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+	},
+	{
+		/* P2 100mts 1D */
+		.drate = 100,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp2_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
+	},
+	{
+		/* P0 2400mts 2D */
+		.drate = 2400,
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = ddr_fsp0_2d_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+	},
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing = {
+	.ddrc_cfg = ddr_ddrc_cfg,
+	.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+	.ddrphy_cfg = ddr_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+	.fsp_msg = ddr_dram_fsp_msg,
+	.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+	.ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+	.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+	.ddrphy_pie = ddr_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+	.fsp_table = { 2400, 400, 100,},
+};
+
diff --git a/board/freescale/imx8mn_evk/imx8mn_evk.c b/board/freescale/imx8mn_evk/imx8mn_evk.c
new file mode 100644
index 0000000000..badfde911b
--- /dev/null
+++ b/board/freescale/imx8mn_evk/imx8mn_evk.c
@@ -0,0 +1,85 @@ 
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx8mn_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/iomux-v3.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_FSEL1)
+#define WDOG_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
+
+static iomux_v3_cfg_t const uart_pads[] = {
+	IMX8MN_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	IMX8MN_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+	IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+};
+
+int board_early_init_f(void)
+{
+	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+
+	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+
+	set_wdog_reset(wdog);
+
+	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+
+	init_uart_clk(1);
+
+	return 0;
+}
+
+#ifdef CONFIG_BOARD_POSTCLK_INIT
+int board_postclk_init(void)
+{
+	/* TODO */
+	return 0;
+}
+#endif
+
+int dram_init(void)
+{
+	/* rom_pointer[1] contains the size of TEE occupies */
+	if (rom_pointer[1])
+		gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1];
+	else
+		gd->ram_size = PHYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	return 0;
+}
+#endif
+
+int board_init(void)
+{
+	return 0;
+}
+
+int board_mmc_get_env_dev(int devno)
+{
+	return devno - 1;
+}
+
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	env_set("board_name", "DDR4 EVK");
+	env_set("board_rev", "iMX8MN");
+#endif
+	return 0;
+}
diff --git a/board/freescale/imx8mn_evk/spl.c b/board/freescale/imx8mn_evk/spl.c
new file mode 100644
index 0000000000..aa5f37fde0
--- /dev/null
+++ b/board/freescale/imx8mn_evk/spl.c
@@ -0,0 +1,90 @@ 
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <asm/arch/imx8mn_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/clock.h>
+#include <asm/gpio.h>
+#include <asm/arch/ddr.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+
+#include <dm/uclass.h>
+#include <dm/device.h>
+#include <dm/uclass-internal.h>
+#include <dm/device-internal.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int spl_board_boot_device(enum boot_device boot_dev_spl)
+{
+	return BOOT_DEVICE_BOOTROM;
+}
+
+void spl_dram_init(void)
+{
+	ddr_init(&dram_timing);
+}
+
+void spl_board_init(void)
+{
+	struct udevice *dev;
+
+	puts("Normal Boot\n");
+
+	uclass_find_first_device(UCLASS_CLK, &dev);
+
+	for (; dev; uclass_find_next_device(&dev)) {
+		if (device_probe(dev))
+			continue;
+	}
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	/* Just empty function now - can't decide what to choose */
+	debug("%s: %s\n", __func__, name);
+
+	return 0;
+}
+#endif
+
+void board_init_f(ulong dummy)
+{
+	int ret;
+
+	arch_cpu_init();
+
+	init_uart_clk(1);
+
+	board_early_init_f();
+
+	timer_init();
+
+	preloader_console_init();
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	ret = spl_init();
+	if (ret) {
+		debug("spl_init() failed: %d\n", ret);
+		hang();
+	}
+
+	enable_tzc380();
+
+	/* DDR initialization */
+	spl_dram_init();
+
+	board_init_r(NULL, 0);
+}
diff --git a/configs/imx8mn_ddr4_evk_defconfig b/configs/imx8mn_ddr4_evk_defconfig
new file mode 100644
index 0000000000..01e10fc427
--- /dev/null
+++ b/configs/imx8mn_ddr4_evk_defconfig
@@ -0,0 +1,53 @@ 
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x6000
+CONFIG_TARGET_IMX8MN_EVK=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL=y
+CONFIG_IMX_ROMAPI_LOADADDR=0x48000000
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mn-ddr4.cfg"
+CONFIG_DEFAULT_FDT_FILE="fsl-imx8mn-ddr4-evk.dtb"
+CONFIG_SPL_TEXT_BASE=0x912000
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_BOOTROM_SUPPORT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mm-evk"
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_IMX8MN=y
+CONFIG_DM_GPIO=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_DM_MMC=y
+CONFIG_PHYLIB=y
+CONFIG_DM_ETH=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_DM_THERMAL=y
diff --git a/include/configs/imx8mn_evk.h b/include/configs/imx8mn_evk.h
new file mode 100644
index 0000000000..6ec8a2e362
--- /dev/null
+++ b/include/configs/imx8mn_evk.h
@@ -0,0 +1,198 @@ 
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#ifndef __IMX8MN_EVK_H
+#define __IMX8MN_EVK_H
+
+#include <linux/sizes.h>
+#include <asm/arch/imx-regs.h>
+
+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_CSF_SIZE			0x2000 /* 8K region */
+#endif
+
+#define CONFIG_SPL_MAX_SIZE		(148 * 1024)
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
+#define CONFIG_SYS_UBOOT_BASE	\
+	(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
+
+#ifdef CONFIG_SPL_BUILD
+/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
+#define CONFIG_SPL_WATCHDOG_SUPPORT
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+#define CONFIG_SPL_POWER_SUPPORT
+#define CONFIG_SPL_LDSCRIPT		"arch/arm/cpu/armv8/u-boot-spl.lds"
+#define CONFIG_SPL_STACK		0x95fff0
+#define CONFIG_SPL_BSS_START_ADDR	0x00950000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x2000	/* 8 KB */
+#define CONFIG_SYS_SPL_MALLOC_START	0x42200000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x80000	/* 64 KB */
+#define CONFIG_SYS_ICACHE_OFF
+#define CONFIG_SYS_DCACHE_OFF
+
+/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
+#define CONFIG_MALLOC_F_ADDR		0x00940000
+
+/* For RAW image gives a error info not panic */
+#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
+
+#undef CONFIG_DM_MMC
+#undef CONFIG_DM_PMIC
+#undef CONFIG_DM_PMIC_PFUZE100
+
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
+#endif
+
+#define CONFIG_REMAKE_ELF
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_POSTCLK_INIT
+#define CONFIG_BOARD_LATE_INIT
+
+/* Flat Device Tree Definitions */
+#define CONFIG_OF_BOARD_SETUP
+
+#undef CONFIG_CMD_EXPORTENV
+#undef CONFIG_CMD_IMPORTENV
+#undef CONFIG_CMD_IMLS
+
+#undef CONFIG_CMD_CRC32
+#undef CONFIG_BOOTM_NETBSD
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"script=boot.scr\0" \
+	"image=Image\0" \
+	"console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200\0" \
+	"fdt_addr=0x43000000\0"			\
+	"fdt_high=0xffffffffffffffff\0"		\
+	"boot_fdt=try\0" \
+	"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
+	"initrd_addr=0x43800000\0"		\
+	"initrd_high=0xffffffffffffffff\0" \
+	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
+	"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+	"mmcautodetect=yes\0" \
+	"mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \
+	"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"booti ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"echo WARN: Cannot load the DT; " \
+			"fi; " \
+		"else " \
+			"echo wait for boot; " \
+		"fi;\0" \
+	"netargs=setenv bootargs console=${console} " \
+		"root=/dev/nfs " \
+		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+	"netboot=echo Booting from net ...; " \
+		"run netargs;  " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${loadaddr} ${image}; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+				"booti ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"echo WARN: Cannot load the DT; " \
+			"fi; " \
+		"else " \
+			"booti; " \
+		"fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+	   "mmc dev ${mmcdev}; if mmc rescan; then " \
+		   "if run loadbootscript; then " \
+			   "run bootscript; " \
+		   "else " \
+			   "if run loadimage; then " \
+				   "run mmcboot; " \
+			   "else run netboot; " \
+			   "fi; " \
+		   "fi; " \
+	   "else booti ${loadaddr} - ${fdt_addr}; fi"
+
+/* Link Definitions */
+#define CONFIG_LOADADDR			0x40480000
+
+#define CONFIG_SYS_LOAD_ADDR           CONFIG_LOADADDR
+
+#define CONFIG_SYS_INIT_RAM_ADDR        0x40000000
+#define CONFIG_SYS_INIT_RAM_SIZE        0x80000
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_ENV_OVERWRITE
+#if defined(CONFIG_ENV_IS_IN_MMC)
+#define CONFIG_ENV_OFFSET               (64 * SZ_64K)
+#endif
+#define CONFIG_ENV_SIZE			0x1000
+#define CONFIG_SYS_MMC_ENV_DEV		0   /* USDHC2 */
+#define CONFIG_MMCROOT			"/dev/mmcblk1p2"  /* USDHC2 */
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		SZ_32M
+
+#define CONFIG_SYS_SDRAM_BASE           0x40000000
+#define PHYS_SDRAM                      0x40000000
+#define PHYS_SDRAM_SIZE			0x80000000 /* 2GB DDR */
+
+#define CONFIG_SYS_MEMTEST_START    PHYS_SDRAM
+#define CONFIG_SYS_MEMTEST_END      (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_SIZE >> 1))
+
+#define CONFIG_BAUDRATE			115200
+
+#define CONFIG_MXC_UART_BASE		UART2_BASE_ADDR
+
+/* Monitor Command Prompt */
+#undef CONFIG_SYS_PROMPT
+#define CONFIG_SYS_PROMPT		"u-boot=> "
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_CBSIZE		2048
+#define CONFIG_SYS_MAXARGS		64
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+
+#define CONFIG_IMX_BOOTAUX
+
+/* USDHC */
+#define CONFIG_CMD_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC
+
+#define CONFIG_SYS_FSL_USDHC_NUM	2
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+
+#define CONFIG_SUPPORT_EMMC_BOOT	/* eMMC specific */
+#define CONFIG_SYS_MMC_IMG_LOAD_PART	1
+
+#define CONFIG_CMD_FUSE
+
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
+#define CONFIG_SYS_I2C_SPEED		100000
+
+#define CONFIG_OF_SYSTEM_SETUP
+#endif