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Mon, 8 Jul 2019 01:39:58 +0000 Received: from AM0PR04MB4481.eurprd04.prod.outlook.com ([fe80::2023:c0e5:8a63:2e47]) by AM0PR04MB4481.eurprd04.prod.outlook.com ([fe80::2023:c0e5:8a63:2e47%5]) with mapi id 15.20.2052.020; Mon, 8 Jul 2019 01:39:58 +0000 From: Peng Fan To: "sbabic@denx.de" , "festevam@gmail.com" Thread-Topic: [PATCH V2 31/51] imx8mq: Update the ddrc QoS setting for B1 chip Thread-Index: AQHVNS4NkfHNhlCcxUyrIjFm5SJstA== Date: Mon, 8 Jul 2019 01:39:58 +0000 Message-ID: <20190708015333.20411-32-peng.fan@nxp.com> References: <20190708015333.20411-1-peng.fan@nxp.com> In-Reply-To: <20190708015333.20411-1-peng.fan@nxp.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.16.4 x-clientproxiedby: HK0PR01CA0059.apcprd01.prod.exchangelabs.com (2603:1096:203:a6::23) To AM0PR04MB4481.eurprd04.prod.outlook.com (2603:10a6:208:70::15) authentication-results: spf=none (sender IP is ) smtp.mailfrom=peng.fan@nxp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [119.31.174.71] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: a019b0b9-3ee8-4995-484d-08d703452f7a x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; 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SFP:1101; SCL:1; SRVR:AM0PR04MB4018; H:AM0PR04MB4481.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: awReQ4M+ghesijNsEqvYQzAx8aK6Nf/VjjTNugYZJcW301v8YP0WNGPZNSwh78bfLB9kIF2JNm6iarPIB+JxJDMHaNOupE7EoeCxkLpZ71//oTFnnaT+OofXNmL4ycCn0S7odk5weMh6zf5PtZun3SMEvqMbz6ermlmCVOoETDXi/0kfFBOSXFRl5Dk5zM4d5bOpIq0eOq2xS6ssormhYDzPeHTdBquHPokB0X7wM/ShBnkGPzeR0/5h3G4fVMydvIyq2DvSKis4FxfR7KdKIpHmC2eJs8qh6e7WkZvnJnte4dgGE/ez/iW1iWAwcO559k48WWRuRO/OfiJFXGuSptqkIW3+ZZtcUZ4ORC2BeIBBHzQvHXSHOnwZnwW3OCIZMfot5lxmXMDvsKSh8y1pELP+ZaRAHNjHMOqmjtoUJDU= MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: a019b0b9-3ee8-4995-484d-08d703452f7a X-MS-Exchange-CrossTenant-originalarrivaltime: 08 Jul 2019 01:39:58.2223 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: peng.fan@nxp.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR04MB4018 Cc: "u-boot@lists.denx.de" , Jacky Bai , dl-uboot-imx Subject: [U-Boot] [PATCH V2 31/51] imx8mq: Update the ddrc QoS setting for B1 chip X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Bai Ping Update the ddrc Qos setting for B1 to align with B0's setting. Correct the initial clock for dram_pll. This setting will be overwrite before ddr phy training. Although there is no impact on the dram init, we still need to correct it to eliminate confusion. Signed-off-by: Bai Ping Reviewed-by: Ye Li Tested-by: Robby Cai --- board/freescale/imx8mq_evk/lpddr4_timing.c | 16 ++++++++++------ drivers/ddr/imx/imx8m/lpddr4_init.c | 5 ++++- 2 files changed, 14 insertions(+), 7 deletions(-) diff --git a/board/freescale/imx8mq_evk/lpddr4_timing.c b/board/freescale/imx8mq_evk/lpddr4_timing.c index f7ea799343..46bc7f8591 100644 --- a/board/freescale/imx8mq_evk/lpddr4_timing.c +++ b/board/freescale/imx8mq_evk/lpddr4_timing.c @@ -72,8 +72,10 @@ struct dram_cfg_param lpddr4_ddrc_cfg[] = { { DDRC_SCHED(0), 0x29511505 }, { DDRC_SCHED1(0), 0x0000002c }, { DDRC_PERFHPR1(0), 0x5900575b }, - { DDRC_PERFLPR1(0), 0x00000009 }, - { DDRC_PERFWR1(0), 0x02005574 }, + /* 150T starve and 0x90 max tran len */ + { DDRC_PERFLPR1(0), 0x90000096 }, + /* 300T starve and 0x10 max tran len */ + { DDRC_PERFWR1(0), 0x1000012c }, { DDRC_DBG0(0), 0x00000016 }, { DDRC_DBG1(0), 0x00000000 }, { DDRC_DBGCMD(0), 0x00000000 }, @@ -83,10 +85,12 @@ struct dram_cfg_param lpddr4_ddrc_cfg[] = { { DDRC_PCFGR_0(0), 0x000010f3 }, { DDRC_PCFGW_0(0), 0x000072ff }, { DDRC_PCTRL_0(0), 0x00000001 }, - { DDRC_PCFGQOS0_0(0), 0x01110d00 }, - { DDRC_PCFGQOS1_0(0), 0x00620790 }, - { DDRC_PCFGWQOS0_0(0), 0x00100001 }, - { DDRC_PCFGWQOS1_0(0), 0x0000041f }, + /* disable Read Qos*/ + { DDRC_PCFGQOS0_0(0), 0x00000e00 }, + { DDRC_PCFGQOS1_0(0), 0x0062ffff }, + /* disable Write Qos*/ + { DDRC_PCFGWQOS0_0(0), 0x00000e00 }, + { DDRC_PCFGWQOS1_0(0), 0x0000ffff }, /* Frequency 1: 400mbps */ { DDRC_FREQ1_DRAMTMG0(0), 0x0d0b010c }, diff --git a/drivers/ddr/imx/imx8m/lpddr4_init.c b/drivers/ddr/imx/imx8m/lpddr4_init.c index a4bc1de8eb..0f46ca02b6 100644 --- a/drivers/ddr/imx/imx8m/lpddr4_init.c +++ b/drivers/ddr/imx/imx8m/lpddr4_init.c @@ -54,7 +54,10 @@ void ddr_init(struct dram_timing_info *dram_timing) reg32setbit(0x303A00F8, 5); /* PU_PGC_SW_PUP_REQ */ debug("DDRINFO: cfg clk\n"); - dram_pll_init(MHZ(750)); + if (is_imx8mq()) + dram_pll_init(MHZ(800)); + else + dram_pll_init(MHZ(750)); /* * release [0]ddr1_preset_n, [1]ddr1_core_reset_n,