diff mbox series

[U-Boot,V2,48/51] clk: imx: add i.MX8MN clk support

Message ID 20190708015333.20411-49-peng.fan@nxp.com
State Rejected
Delegated to: Stefano Babic
Headers show
Series Support i.MX8MM/N | expand

Commit Message

Peng Fan July 8, 2019, 1:40 a.m. UTC 
Reuse i.MX8MM clk driver for i.MX8MN.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/clk/imx/Kconfig      |  7 +++++++
 drivers/clk/imx/Makefile     |  2 +-
 drivers/clk/imx/clk-imx8mm.c | 15 +++++++++++++++
 3 files changed, 23 insertions(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig
index 07ecad0a72..4beaaf507b 100644
--- a/drivers/clk/imx/Kconfig
+++ b/drivers/clk/imx/Kconfig
@@ -11,3 +11,10 @@  config CLK_IMX8MM
 	select CLK
 	help
 	  This enables support clock driver for i.MX8 platforms.
+
+config CLK_IMX8MN
+	bool "Clock support for i.MX8MM"
+	depends on IMX8MN
+	select CLK
+	help
+	  This enables support clock driver for i.MX8MN platforms.
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index b55566f2e9..1d30c5be6b 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -8,4 +8,4 @@  ifdef CONFIG_CLK_IMX8
 obj-$(CONFIG_IMX8QXP) += clk-imx8qxp.o
 obj-$(CONFIG_IMX8QM) += clk-imx8qm.o
 endif
-obj-$(CONFIG_CLK_IMX8MM) += clk-imx8mm.o
+obj-$(CONFIG_CLK_IMX8MM)$(CONFIG_CLK_IMX8MN) += clk-imx8mm.o
diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
index 1e0669494f..e0b7d0fdc9 100644
--- a/drivers/clk/imx/clk-imx8mm.c
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -9,6 +9,7 @@ 
 #include <dm.h>
 #include <asm/arch/clock.h>
 #include <dt-bindings/clock/imx8mm-clock.h>
+#include <dt-bindings/clock/imx8mn-clock.h>
 
 static ulong imx8mm_clk_get_rate(struct clk *clk)
 {
@@ -16,17 +17,24 @@  static ulong imx8mm_clk_get_rate(struct clk *clk)
 
 	switch (clk->id) {
 	case IMX8MM_CLK_USDHC1_ROOT:
+	case IMX8MN_CLK_USDHC1_ROOT:
 		return get_root_clk(USDHC1_CLK_ROOT);
+	case IMX8MN_CLK_USDHC2_ROOT:
 	case IMX8MM_CLK_USDHC2_ROOT:
 		return get_root_clk(USDHC2_CLK_ROOT);
+	case IMX8MN_CLK_USDHC3_ROOT:
 	case IMX8MM_CLK_USDHC3_ROOT:
 		return get_root_clk(USDHC3_CLK_ROOT);
+	case IMX8MN_CLK_I2C1:
 	case IMX8MM_CLK_I2C1:
 		return get_root_clk(I2C1_CLK_ROOT);
+	case IMX8MN_CLK_I2C2:
 	case IMX8MM_CLK_I2C2:
 		return get_root_clk(I2C2_CLK_ROOT);
+	case IMX8MN_CLK_I2C3:
 	case IMX8MM_CLK_I2C3:
 		return get_root_clk(I2C3_CLK_ROOT);
+	case IMX8MN_CLK_I2C4:
 	case IMX8MM_CLK_I2C4:
 		return get_root_clk(I2C4_CLK_ROOT);
 	}
@@ -37,18 +45,25 @@  static ulong imx8mm_clk_get_rate(struct clk *clk)
 static int __imx8mm_clk_enable(struct clk *clk, bool enable)
 {
 	switch (clk->id) {
+	case IMX8MN_CLK_USDHC1_ROOT:
 	case IMX8MM_CLK_USDHC1_ROOT:
 		return clock_enable(CCGR_USDHC1, enable);
+	case IMX8MN_CLK_USDHC2_ROOT:
 	case IMX8MM_CLK_USDHC2_ROOT:
 		return clock_enable(CCGR_USDHC2, enable);
+	case IMX8MN_CLK_USDHC3_ROOT:
 	case IMX8MM_CLK_USDHC3_ROOT:
 		return clock_enable(CCGR_USDHC3, enable);
+	case IMX8MN_CLK_I2C1:
 	case IMX8MM_CLK_I2C1:
 		return clock_enable(CCGR_I2C1, enable);
+	case IMX8MN_CLK_I2C2:
 	case IMX8MM_CLK_I2C2:
 		return clock_enable(CCGR_I2C2, enable);
+	case IMX8MN_CLK_I2C3:
 	case IMX8MM_CLK_I2C3:
 		return clock_enable(CCGR_I2C3, enable);
+	case IMX8MN_CLK_I2C4:
 	case IMX8MM_CLK_I2C4:
 		return clock_enable(CCGR_I2C4, enable);
 	}