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SFP:1101; SCL:1; SRVR:AM0PR04MB5906; H:AM0PR04MB4481.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: iPqtX2NhWD3EWQCJTMj75fc/93bB5trpii5xR4ZbJ0odbnQYWrds9R7jzj2wXg0GJIGj0XBY5NKXP9iaMJ3VqRnIu3obVvVQCaAam9dUxUMdeMlYr6IUC4SFdBUSJwzwUITAYFURptFKbBeCvLavWD2K1YOTIIbNCkQVkIiNNzNijvO5XU6yZavVbnMhImvsv2h1CZZZJ79YH9BL1IVmdFs/eszTRFd8+f8RLmFv3/ST9u2UR/I3cJy9o37o8908p17ezGjq06JjXPnTwGgLahTOFAFnpielC/DNb0N7hG8Hmq7yxNA/hCMjOy4z5W72+BcGU/sEd5BDsoIzm8Ti2vpp4ug7HVnn/95abYnggv5+o6kqgCoTjVRnZ4DnC8awGjP1V+J7Blc9H60ma8TxJzUNi1RuiG4jsPyIz9glUfI= MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 983be9bb-b3c0-4a4a-4c7d-08d70345386b X-MS-Exchange-CrossTenant-originalarrivaltime: 08 Jul 2019 01:40:13.4365 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: peng.fan@nxp.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR04MB5906 Cc: "u-boot@lists.denx.de" , dl-uboot-imx Subject: [U-Boot] [PATCH V2 37/51] imx8mn: set BYPASS ID SWAP to avoid AXI bus errors X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Set the BYPASS ID SWAP bit (GPR10 bit 1) in order for GPU not to generated AXI bus errors with TZC380 enabled. Signed-off-by: Peng Fan --- arch/arm/mach-imx/imx8m/soc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index a8cb6ca31c..98896893c9 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -59,7 +59,7 @@ void enable_tzc380(void) /* Enable TZASC and lock setting */ setbits_le32(&gpr->gpr[10], GPR_TZASC_EN); setbits_le32(&gpr->gpr[10], GPR_TZASC_EN_LOCK); - if (IS_ENABLED(CONFIG_IMX8MM)) + if (is_imx8mm() || is_imx8mn()) setbits_le32(&gpr->gpr[10], BIT(1)); /* * set Region 0 attribute to allow secure and non-secure