@@ -36,6 +36,7 @@
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <asm/mach-types.h>
+#include <asm/psci.h>
#include <asm/setup.h>
#include "board.h"
@@ -92,6 +93,9 @@ static void __init tegra_dt_init_late(void)
if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) &&
of_machine_is_compatible("nvidia,tegra20"))
platform_device_register_simple("tegra20-cpufreq", -1, NULL, 0);
+
+ if (IS_ENABLED(CONFIG_ARM_TEGRA_CPUIDLE) && !psci_smp_available())
+ platform_device_register_simple("tegra-cpuidle", -1, NULL, 0);
}
static const char * const tegra_dt_board_compat[] = {
@@ -76,3 +76,11 @@ config ARM_MVEBU_V7_CPUIDLE
depends on ARCH_MVEBU && !ARM64
help
Select this to enable cpuidle on Armada 370, 38x and XP processors.
+
+config ARM_TEGRA_CPUIDLE
+ bool "CPU Idle Driver for NVIDIA Tegra SoCs"
+ depends on ARCH_TEGRA && !ARM64
+ select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP
+ select ARM_CPU_SUSPEND
+ help
+ Select this to enable cpuidle for NVIDIA Tegra20/30/114/124 SoCs.
@@ -20,6 +20,7 @@ obj-$(CONFIG_ARM_U8500_CPUIDLE) += cpuidle-ux500.o
obj-$(CONFIG_ARM_AT91_CPUIDLE) += cpuidle-at91.o
obj-$(CONFIG_ARM_EXYNOS_CPUIDLE) += cpuidle-exynos.o
obj-$(CONFIG_ARM_CPUIDLE) += cpuidle-arm.o
+obj-$(CONFIG_ARM_TEGRA_CPUIDLE) += cpuidle-tegra.o
###############################################################################
# MIPS drivers
new file mode 100644
@@ -0,0 +1,237 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * CPU idle driver for Tegra CPUs
+ *
+ * Copyright (c) 2010-2013, NVIDIA Corporation.
+ * Copyright (c) 2011 Google, Inc.
+ * Author: Colin Cross <ccross@android.com>
+ * Gary King <gking@nvidia.com>
+ *
+ * Rework for 3.3 by Peter De Schrijver <pdeschrijver@nvidia.com>
+ *
+ * Tegra20-124 driver unification by Dmitry Osipenko <digetx@gmail.com>
+ */
+
+#include <linux/cpuidle.h>
+#include <linux/cpumask.h>
+#include <linux/cpu_pm.h>
+#include <linux/errno.h>
+#include <linux/platform_device.h>
+
+#include <linux/clk/tegra.h>
+#include <linux/firmware/trusted_foundations.h>
+
+#include <soc/tegra/cpuidle.h>
+#include <soc/tegra/flowctrl.h>
+#include <soc/tegra/fuse.h>
+#include <soc/tegra/pm.h>
+
+#include <asm/cpuidle.h>
+#include <asm/firmware.h>
+#include <asm/smp_plat.h>
+#include <asm/suspend.h>
+
+static atomic_t tegra_idle_barrier;
+
+static int tegra_shutdown_secondary_cpu(unsigned long cpu)
+{
+ tegra_cpu_die(cpu);
+
+ return -EINVAL;
+}
+
+static void tegra_await_secondary_cpus(void)
+{
+ /*
+ * The boot CPU shall await for the secondaries shutdown in order
+ * to power-off CPU's cluster safely.
+ */
+ while (!tegra_cpu_rail_off_ready())
+ cpu_relax();
+}
+
+static void tegra_wake_up_secondary_cpus(void)
+{
+ unsigned int cpu, lcpu;
+
+ for_each_cpu(lcpu, cpu_online_mask) {
+ cpu = cpu_logical_map(lcpu);
+
+ if (cpu > 0) {
+ tegra_enable_cpu_clock(cpu);
+ tegra_cpu_out_of_reset(cpu);
+ flowctrl_write_cpu_halt(cpu, 0);
+ }
+ }
+}
+
+static int tegra_cpu_idle(struct cpuidle_device *dev,
+ struct cpuidle_driver *drv,
+ int index)
+{
+ unsigned int cpu = cpu_logical_map(dev->cpu);
+ int err;
+
+ /*
+ * On Tegra30 CPU0 can't be power-gated while secondary CPUs
+ * are active because it gates the whole CPU cluster.
+ */
+ if (index == 1 && cpu == 0)
+ return arm_cpuidle_simple_enter(dev, drv, 0);
+
+ local_fiq_disable();
+ tegra_set_cpu_in_lp2();
+ cpu_pm_enter();
+
+ switch (index) {
+ case 1:
+ err = cpu_suspend(0, tegra30_sleep_cpu_secondary_finish);
+ break;
+ case 2:
+ cpuidle_coupled_parallel_barrier(dev, &tegra_idle_barrier);
+
+ if (cpu == 0) {
+ tegra_await_secondary_cpus();
+ err = tegra_idle_lp2_last();
+ tegra_wake_up_secondary_cpus();
+ } else {
+ err = cpu_suspend(cpu, tegra_shutdown_secondary_cpu);
+ }
+ break;
+ case 3:
+ err = call_firmware_op(prepare_idle, TF_PM_MODE_LP2_NOFLUSH_L2);
+ if (err && err != -ENOSYS)
+ break;
+
+ err = call_firmware_op(do_idle, 0);
+ if (err && err != -ENOSYS)
+ break;
+
+ /*
+ * Do suspend by ourselves if the firmware does not
+ * implement it.
+ */
+ err = cpu_suspend(0, tegra30_sleep_cpu_secondary_finish);
+ break;
+ default:
+ err = -EINVAL;
+ break;
+ }
+
+ cpu_pm_exit();
+ tegra_clear_cpu_in_lp2();
+ local_fiq_enable();
+
+ smp_rmb();
+
+ return WARN_ON_ONCE(err) ? -1 : index;
+}
+
+static void tegra114_idle_enter_s2idle(struct cpuidle_device *dev,
+ struct cpuidle_driver *drv,
+ int index)
+{
+ tegra_cpu_idle(dev, drv, index);
+}
+
+static struct cpuidle_driver tegra_idle_driver = {
+ .name = "tegra_idle",
+ .states = {
+ [0] = ARM_CPUIDLE_WFI_STATE_PWR(600),
+ [1] = {
+ .enter = tegra_cpu_idle,
+ .exit_latency = 2000,
+ .target_residency = 2200,
+ .power_usage = 0,
+ .flags = CPUIDLE_FLAG_TIMER_STOP,
+ .name = "powered-down",
+ .desc = "CPU core powered-off",
+ },
+ [2] = {
+ .enter = tegra_cpu_idle,
+ .exit_latency = 5000,
+ .target_residency = 10000,
+ .power_usage = 0,
+ .flags = CPUIDLE_FLAG_COUPLED |
+ CPUIDLE_FLAG_TIMER_STOP,
+ .name = "powered-down",
+ .desc = "CPU cluster powered-off",
+ },
+ [3] = {
+ .enter = tegra_cpu_idle,
+ .enter_s2idle = tegra114_idle_enter_s2idle,
+ .exit_latency = 500,
+ .target_residency = 1000,
+ .power_usage = 0,
+ .flags = CPUIDLE_FLAG_TIMER_STOP,
+ .name = "powered-down",
+ .desc = "CPU core power-gated",
+ },
+ },
+ .state_count = 4,
+ .safe_state_index = 0,
+};
+
+/*
+ * Tegra20 HW appears to have a bug such that PCIe device interrupts, whether
+ * they are legacy IRQs or MSI, are lost when LP2 is enabled. To work around
+ * this, simply disable LP2 if the PCI driver and DT node are both enabled.
+ */
+void tegra_cpuidle_pcie_irqs_in_use(void)
+{
+ if (tegra_get_chip_id() != TEGRA20 ||
+ tegra_idle_driver.states[2].disabled)
+ return;
+
+ pr_info("Disabling cpuidle LP2 state, since PCIe IRQs are in use\n");
+ tegra_idle_driver.states[2].disabled = true;
+}
+
+static int tegra_cpuidle_probe(struct platform_device *pdev)
+{
+ const struct cpumask *coupled_cpus = cpu_possible_mask;
+
+ /*
+ * Generic WFI state is common for all NVIDIA Tegra SoCs.
+ *
+ * Secondary CPU core can't be power-gated separately from CPU0
+ * on Tegra20.
+ *
+ * On Tegra114/124 all CPU cores could be power-gated separately.
+ */
+ switch (tegra_get_chip_id()) {
+ case TEGRA20:
+ tegra_idle_driver.states[1].disabled = true;
+ tegra_idle_driver.states[3].disabled = true;
+ break;
+ case TEGRA30:
+ tegra_idle_driver.states[2].disabled = true;
+ tegra_idle_driver.states[3].disabled = true;
+ break;
+ case TEGRA114:
+ case TEGRA124:
+ tegra_idle_driver.states[1].disabled = true;
+ tegra_idle_driver.states[2].disabled = true;
+
+ coupled_cpus = NULL;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ if (!IS_ENABLED(CONFIG_PM_SLEEP)) {
+ tegra_idle_driver.states[1].disabled = true;
+ tegra_idle_driver.states[2].disabled = true;
+ }
+
+ return cpuidle_register(&tegra_idle_driver, coupled_cpus);
+}
+
+static struct platform_driver tegra_cpuidle_driver = {
+ .probe = tegra_cpuidle_probe,
+ .driver = {
+ .name = "tegra-cpuidle",
+ .suppress_bind_attrs = true,
+ },
+};
+builtin_platform_driver(tegra_cpuidle_driver);
@@ -6,8 +6,12 @@
#ifndef __SOC_TEGRA_CPUIDLE_H__
#define __SOC_TEGRA_CPUIDLE_H__
+#ifdef CONFIG_ARM_TEGRA_CPUIDLE
+void tegra_cpuidle_pcie_irqs_in_use(void);
+#else
static inline void tegra_cpuidle_pcie_irqs_in_use(void)
{
}
+#endif
#endif /* __SOC_TEGRA_CPUIDLE_H__ */
The new driver is based on the old CPU Idle drivers that are removed now from arm/arch/mach-tegra/ directory. Those removed drivers were reworked and squashed into a single unified driver that covers multiple hardware generations, starting from Tegra20 and ending with Tegra124. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> --- arch/arm/mach-tegra/tegra.c | 4 + drivers/cpuidle/Kconfig.arm | 8 ++ drivers/cpuidle/Makefile | 1 + drivers/cpuidle/cpuidle-tegra.c | 237 ++++++++++++++++++++++++++++++++ include/soc/tegra/cpuidle.h | 4 + 5 files changed, 254 insertions(+) create mode 100644 drivers/cpuidle/cpuidle-tegra.c