@@ -64,8 +64,12 @@ int sc_pm_get_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk,
sc_pm_clock_rate_t *rate);
int sc_pm_clock_enable(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk,
sc_bool_t enable, sc_bool_t autog);
+int sc_pm_set_clock_parent(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk,
+ sc_pm_clk_parent_t parent);
/* MISC API */
+int sc_misc_set_control(sc_ipc_t ipc, sc_rsrc_t resource,
+ sc_ctrl_t ctrl, u32 val);
int sc_misc_get_control(sc_ipc_t ipc, sc_rsrc_t resource, sc_ctrl_t ctrl,
u32 *val);
void sc_misc_get_boot_dev(sc_ipc_t ipc, sc_rsrc_t *boot_dev);
@@ -35,6 +35,13 @@
#define SC_PM_CLK_MODE_AUTOGATE_HW 4U /* Clock is in HW autogate mode */
#define SC_PM_CLK_MODE_AUTOGATE_SW_HW 5U /* Clock is in SW-HW autogate mode */
+/* Defines for sc_pm_clk_parent_t */
+#define SC_PM_PARENT_XTAL 0U /*!< Parent is XTAL. */
+#define SC_PM_PARENT_PLL0 1U /*!< Parent is PLL0 */
+#define SC_PM_PARENT_PLL1 2U /*!< Parent is PLL1 or PLL0/2 */
+#define SC_PM_PARENT_PLL2 3U /*!< Parent in PLL2 or PLL0/4 */
+#define SC_PM_PARENT_BYPS 4U /*!< Parent is a bypass clock. */
+
typedef u8 sc_pm_power_mode_t;
typedef u8 sc_pm_clk_t;
typedef u8 sc_pm_clk_mode_t;
@@ -185,7 +185,18 @@ typedef u64 sc_ipc_t;
#define SC_C_RST0 43U
#define SC_C_RST1 44U
#define SC_C_SEL0 45U
-#define SC_C_LAST 46U
+#define SC_C_CALIB0 46U
+#define SC_C_CALIB1 47U
+#define SC_C_CALIB2 48U
+#define SC_C_IPG_DEBUG 49U
+#define SC_C_IPG_DOZE 50U
+#define SC_C_IPG_WAIT 51U
+#define SC_C_IPG_STOP 52U
+#define SC_C_IPG_STOP_MODE 53U
+#define SC_C_IPG_STOP_ACK 54U
+#define SC_C_SYNC_CTRL 55U
+#define SC_C_LAST 56U
+
#define SC_P_ALL ((sc_pad_t)UINT16_MAX) /* All pads */
@@ -93,6 +93,31 @@ int sc_pm_clock_enable(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk,
return ret;
}
+int sc_pm_set_clock_parent(sc_ipc_t ipc, sc_rsrc_t resource,
+ sc_pm_clk_t clk, sc_pm_clk_parent_t parent)
+{
+ struct udevice *dev = gd->arch.scu_dev;
+ int size = sizeof(struct sc_rpc_msg_s);
+ struct sc_rpc_msg_s msg;
+ int ret;
+
+ RPC_VER(&msg) = SC_RPC_VERSION;
+ RPC_SVC(&msg) = (u8)(SC_RPC_SVC_PM);
+ RPC_FUNC(&msg) = (u8)(PM_FUNC_SET_CLOCK_PARENT);
+ RPC_U16(&msg, 0U) = (u16)(resource);
+ RPC_U8(&msg, 2U) = (u8)(clk);
+ RPC_U8(&msg, 3U) = (u8)(parent);
+ RPC_SIZE(&msg) = 2U;
+
+ ret = misc_call(dev, SC_FALSE, &msg, size, &msg, size);
+ if (ret)
+ printf("%s: resource:%d clk:%d: parent clk: %d, res:%d\n",
+ __func__, resource, clk, parent, RPC_R8(&msg));
+
+ return ret;
+}
+
+
int sc_pm_set_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
sc_pm_power_mode_t mode)
{
@@ -146,6 +171,33 @@ int sc_pad_set(sc_ipc_t ipc, sc_pad_t pad, u32 val)
}
/* MISC */
+int sc_misc_set_control(sc_ipc_t ipc, sc_rsrc_t resource,
+ sc_ctrl_t ctrl, u32 val)
+{
+ struct udevice *dev = gd->arch.scu_dev;
+ int size = sizeof(struct sc_rpc_msg_s);
+ struct sc_rpc_msg_s msg;
+ int ret;
+
+ if (!dev)
+ hang();
+
+ RPC_VER(&msg) = SC_RPC_VERSION;
+ RPC_SVC(&msg) = (u8)(SC_RPC_SVC_MISC);
+ RPC_FUNC(&msg) = (u8)(MISC_FUNC_SET_CONTROL);
+ RPC_U32(&msg, 0U) = (u32)(ctrl);
+ RPC_U32(&msg, 4U) = (u32)(val);
+ RPC_U16(&msg, 8U) = (u16)(resource);
+ RPC_SIZE(&msg) = 4U;
+
+ ret = misc_call(dev, SC_FALSE, &msg, size, &msg, size);
+ if (ret)
+ printf("%s: ctrl:%d resource:%d: res:%d\n",
+ __func__, ctrl, resource, RPC_R8(&msg));
+
+ return ret;
+}
+
int sc_misc_get_control(sc_ipc_t ipc, sc_rsrc_t resource, sc_ctrl_t ctrl,
u32 *val)
{
@@ -554,4 +554,6 @@
#define SC_R_VPU 540
#define SC_R_LAST 541
+#define SC_R_NONE 0xFFF0
+
#endif /* DT_BINDINGS_RSCRC_IMX_H */
Add sc_misc_set_control to write the subsystem's DSC GPR registers, and sc_pm_set_clock_parent to select parent clock source. Signed-off-by: Ye Li <ye.li@nxp.com> --- Changes in v2: - None arch/arm/include/asm/arch-imx8/sci/sci.h | 4 ++ arch/arm/include/asm/arch-imx8/sci/svc/pm/api.h | 7 ++++ arch/arm/include/asm/arch-imx8/sci/types.h | 13 ++++++- drivers/misc/imx8/scu_api.c | 52 +++++++++++++++++++++++++ include/dt-bindings/soc/imx_rsrc.h | 2 + 5 files changed, 77 insertions(+), 1 deletion(-)