From patchwork Wed Jul 3 05:40:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ye Li X-Patchwork-Id: 1126625 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=nxp.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=nxp.com header.i=@nxp.com header.b="B8tMGdeB"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 45dqhJ0Bkmz9s3Z for ; Wed, 3 Jul 2019 15:40:31 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 3BE1BC21DDC; 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Wed, 3 Jul 2019 05:40:22 +0000 Received: from VI1PR04MB4414.eurprd04.prod.outlook.com ([fe80::6517:7774:1033:6466]) by VI1PR04MB4414.eurprd04.prod.outlook.com ([fe80::6517:7774:1033:6466%7]) with mapi id 15.20.2032.019; Wed, 3 Jul 2019 05:40:22 +0000 From: Ye Li To: "sbabic@denx.de" , Fabio Estevam , Peng Fan Thread-Topic: [PATCH 1/5] imx8: Add lpcg driver for iMX8QM/QXP Thread-Index: AQHVMWHOkK6l09/9dUe53Wv9nrEavA== Date: Wed, 3 Jul 2019 05:40:21 +0000 Message-ID: <1562132399-114515-1-git-send-email-ye.li@nxp.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.7.4 x-clientproxiedby: HK0PR01CA0013.apcprd01.prod.exchangelabs.com (2603:1096:203:92::25) To VI1PR04MB4414.eurprd04.prod.outlook.com (2603:10a6:803:6e::25) authentication-results: spf=none (sender IP is ) smtp.mailfrom=ye.li@nxp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [119.31.174.68] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: a64b2a95-7565-4eb1-e6f6-08d6ff78ee17 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600148)(711020)(4605104)(1401327)(4618075)(2017052603328)(7193020); SRVR:VI1PR04MB5134; x-ms-traffictypediagnostic: VI1PR04MB5134: x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:215; x-forefront-prvs: 00872B689F x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(4636009)(396003)(346002)(136003)(376002)(366004)(39860400002)(189003)(199004)(66066001)(81166006)(81156014)(2906002)(14454004)(476003)(486006)(3846002)(36756003)(2501003)(44832011)(4326008)(305945005)(8676002)(14444005)(86362001)(30864003)(6116002)(7736002)(186003)(8936002)(71200400001)(71190400001)(2616005)(53936002)(256004)(99286004)(110136005)(52116002)(5660300002)(6512007)(26005)(6506007)(66476007)(316002)(25786009)(478600001)(54906003)(53946003)(102836004)(50226002)(66946007)(68736007)(6486002)(64756008)(66556008)(66446008)(386003)(6636002)(6436002)(73956011)(32563001); DIR:OUT; SFP:1101; SCL:1; SRVR:VI1PR04MB5134; H:VI1PR04MB4414.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: zcCR5jHDRdMuqnzO6aeHVjguZzzSwnaF5H2vfkYzCUvwDZ1CT/SOJAhoBFs+fIoF2bf66HHPJfyArnyQrM/8GBE+2hYm7GLGey/xLssvzPUQXehrjv9oMyln28Nw3C2Retpl4/PJWeoRksMYyO7Zmqu1XRMMIZrOGfTb1essUhdG7V8i9vWig2zVpKodo1X0vGOkFRg1pgEzNCdIK4ac+0+Ru+iJqllFv2V5wiN8IwDfMl6CdrIb0b+3bXqEx7zUPT3nJen0F2Dn3mNrgBKKE8/wL7oPL8a2D7ZRWNvwnjcPSP0WvKa6MwUttD34XEpYPpVR//cmmfgNLmkb3Zc5wt5MMMIbnHmQGClARpNKVuylT4hxVpu3170tJo76luevrLLfTy81EN1D9+U0b+phe8ODY+hN7f5pVSfFzCjMpr4= MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: a64b2a95-7565-4eb1-e6f6-08d6ff78ee17 X-MS-Exchange-CrossTenant-originalarrivaltime: 03 Jul 2019 05:40:21.9331 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: ye.li@nxp.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB5134 Cc: "u-boot@lists.denx.de" , dl-uboot-imx Subject: [U-Boot] [PATCH 1/5] imx8: Add lpcg driver for iMX8QM/QXP X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Each module may have one or more lpcg registers for SW/HW enabling its clocks. Add lpcg register address and its driver for accessing lpcg. Signed-off-by: Ye Li --- arch/arm/include/asm/arch-imx8/imx8qm_lpcg.h | 200 ++++++++++++++++++++++++++ arch/arm/include/asm/arch-imx8/imx8qxp_lpcg.h | 195 +++++++++++++++++++++++++ arch/arm/include/asm/arch-imx8/lpcg.h | 26 ++++ arch/arm/mach-imx/imx8/Makefile | 2 +- arch/arm/mach-imx/imx8/lpcg.c | 115 +++++++++++++++ 5 files changed, 537 insertions(+), 1 deletion(-) create mode 100644 arch/arm/include/asm/arch-imx8/imx8qm_lpcg.h create mode 100644 arch/arm/include/asm/arch-imx8/imx8qxp_lpcg.h create mode 100644 arch/arm/include/asm/arch-imx8/lpcg.h create mode 100644 arch/arm/mach-imx/imx8/lpcg.c diff --git a/arch/arm/include/asm/arch-imx8/imx8qm_lpcg.h b/arch/arm/include/asm/arch-imx8/imx8qm_lpcg.h new file mode 100644 index 0000000..692c27f --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/imx8qm_lpcg.h @@ -0,0 +1,200 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SC_LPCG_H +#define _SC_LPCG_H + +/*LSIO SS */ +#define PWM_0_LPCG 0x5D400000 +#define PWM_1_LPCG 0x5D410000 +#define PWM_2_LPCG 0x5D420000 +#define PWM_3_LPCG 0x5D430000 +#define PWM_4_LPCG 0x5D440000 +#define PWM_5_LPCG 0x5D450000 +#define PWM_6_LPCG 0x5D460000 +#define PWM_7_LPCG 0x5D470000 +#define GPIO_0_LPCG 0x5D480000 +#define GPIO_1_LPCG 0x5D490000 +#define GPIO_2_LPCG 0x5D4A0000 +#define GPIO_3_LPCG 0x5D4B0000 +#define GPIO_4_LPCG 0x5D4C0000 +#define GPIO_5_LPCG 0x5D4D0000 +#define GPIO_6_LPCG 0x5D4E0000 +#define GPIO_7_LPCG 0x5D4F0000 +#define FSPI_0_LPCG 0x5D520000 +#define FSPI_1_LPCG 0x5D530000 +#define GPT_0_LPCG 0x5D540000 +#define GPT_1_LPCG 0x5D550000 +#define GPT_2_LPCG 0x5D560000 +#define GPT_3_LPCG 0x5D570000 +#define GPT_4_LPCG 0x5D580000 +#define OCRAM_LPCG 0x5D590000 +#define KPP_LPCG 0x5D5A0000 +#define MU_5A_LPCG 0x5D600000 +#define MU_6A_LPCG 0x5D610000 +#define MU_7A_LPCG 0x5D620000 +#define MU_8A_LPCG 0x5D630000 +#define MU_9A_LPCG 0x5D640000 +#define MU_10A_LPCG 0x5D650000 +#define MU_11A_LPCG 0x5D660000 +#define MU_12A_LPCG 0x5D670000 +#define MU_13A_LPCG 0x5D680000 + +/* HSIO SS */ +#define CRR_5_LPCG 0x5F0F0000 +#define CRR_4_LPCG 0x5F0E0000 +#define CRR_3_LPCG 0x5F0D0000 +#define CRR_2_LPCG 0x5F0C0000 +#define CRR_1_LPCG 0x5F0B0000 +#define CRR_0_LPCG 0x5F0A0000 +#define PHY_1_LPCG 0x5F090000 +#define PHY_2_LPCG 0x5F080000 +#define SATA_0_LPCG 0x5F070000 +#define PCIE_B_LPCG 0x5F060000 +#define PCIE_A_LPCG 0x5F050000 + +/* DMA SS */ +#define FLEX_CAN_2_LPCG 0x5ACF0000 +#define FLEX_CAN_1_LPCG 0x5ACE0000 +#define FLEX_CAN_0_LPCG 0x5ACD0000 +#define FTM_1_LPCG 0x5ACB0000 +#define FTM_0_LPCG 0x5ACA0000 +#define ADC_1_LPCG 0x5AC90000 +#define ADC_0_LPCG 0x5AC80000 +#define LPI2C_4_LPCG 0x5AC40000 +#define LPI2C_3_LPCG 0x5AC30000 +#define LPI2C_2_LPCG 0x5AC20000 +#define LPI2C_1_LPCG 0x5AC10000 +#define LPI2C_0_LPCG 0x5AC00000 +#define EMVSIM_1_LPCG 0x5A4E0000 +#define EMVSIM_0_LPCG 0x5A4D0000 +#define LPUART_4_LPCG 0x5A4A0000 +#define LPUART_3_LPCG 0x5A490000 +#define LPUART_2_LPCG 0x5A480000 +#define LPUART_1_LPCG 0x5A470000 +#define LPUART_0_LPCG 0x5A460000 +#define LPSPI_3_LPCG 0x5A430000 +#define LPSPI_2_LPCG 0x5A420000 +#define LPSPI_1_LPCG 0x5A410000 +#define LPSPI_0_LPCG 0x5A400000 + +/* Display SS */ +#define DC_0_LPCG 0x56010000 +#define DC_1_LPCG 0x57010000 + +/* LVDS */ +#define DI_LVDS_0_LPCG 0x56243000 +#define DI_LVDS_1_LPCG 0x57243000 + +/* DI HDMI */ +#define DI_HDMI_LPCG 0x56263000 + +/* RX-HDMI */ +#define RX_HDMI_LPCG 0x58263000 + +/* MIPI CSI SS */ +#define MIPI_CSI_0_LPCG 0x58223000 +#define MIPI_CSI_1_LPCG 0x58243000 + +/* MIPI DSI SS */ +#define MIPI_DSI_0_LPCG 0x56223000 +#define MIPI_DSI_1_LPCG 0x57223000 + +/* Imaging SS */ +#define IMG_JPEG_ENC_LPCG 0x585F0000 +#define IMG_JPEG_DEC_LPCG 0x585D0000 +#define IMG_PXL_LINK_DC1_LPCG 0x585C0000 +#define IMG_PXL_LINK_DC0_LPCG 0x585B0000 +#define IMG_PXL_LINK_HDMI_LPCG 0x585A0000 +#define IMG_PXL_LINK_CSI1_LPCG 0x58590000 +#define IMG_PXL_LINK_CSI0_LPCG 0x58580000 +#define IMG_PDMA_7_LPCG 0x58570000 +#define IMG_PDMA_6_LPCG 0x58560000 +#define IMG_PDMA_5_LPCG 0x58550000 +#define IMG_PDMA_4_LPCG 0x58540000 +#define IMG_PDMA_3_LPCG 0x58530000 +#define IMG_PDMA_2_LPCG 0x58520000 +#define IMG_PDMA_1_LPCG 0x58510000 +#define IMG_PDMA_0_LPCG 0x58500000 + +/* HSIO SS */ +#define HSIO_GPIO_LPCG 0x5F100000 +#define HSIO_MISC_LPCG 0x5F0F0000 +#define HSIO_SATA_CRR4_LPCG 0x5F0E0000 +#define HSIO_PCIE_X1_CRR3_LPCG 0x5F0D0000 +#define HSIO_PCIE_X2_CRR2_LPCG 0x5F0C0000 +#define HSIO_PHY_X1_CRR1_LPCG 0x5F0B0000 +#define HSIO_PHY_X2_CRR0_LPCG 0x5F0A0000 +#define HSIO_PHY_X1_LPCG 0x5F090000 +#define HSIO_PHY_X2_LPCG 0x5F080000 +#define HSIO_SATA_LPCG 0x5F070000 +#define HSIO_PCIE_X1_LPCG 0x5F060000 +#define HSIO_PCIE_X2_LPCG 0x5F050000 + +/* M4 SS */ +#define M4_0_I2C_LPCG 0x37630000 +#define M4_0_LPUART_LPCG 0x37620000 +#define M4_0_LPIT_LPCG 0x37610000 +#define M4_1_I2C_LPCG 0x3B630000 +#define M4_1_LPUART_LPCG 0x3B620000 +#define M4_1_LPIT_LPCG 0x3B610000 + +/* Audio SS */ +#define AUD_ASRC_0_LPCG 0x59400000 +#define AUD_ESAI_0_LPCG 0x59410000 +#define AUD_SPDIF_0_LPCG 0x59420000 +#define AUD_SPDIF_1_LPCG 0x59430000 +#define AUD_SAI_0_LPCG 0x59440000 +#define AUD_SAI_1_LPCG 0x59450000 +#define AUD_SAI_2_LPCG 0x59460000 +#define AUD_SAI_3_LPCG 0x59470000 +#define AUD_HDMI_RX_SAI_0_LPCG 0x59480000 +#define AUD_HDMI_TX_SAI_0_LPCG 0x59490000 +#define AUD_GPT_5_LPCG 0x594B0000 +#define AUD_GPT_6_LPCG 0x594C0000 +#define AUD_GPT_7_LPCG 0x594D0000 +#define AUD_GPT_8_LPCG 0x594E0000 +#define AUD_GPT_9_LPCG 0x594F0000 +#define AUD_GPT_10_LPCG 0x59500000 +#define AUD_DSP_LPCG 0x59580000 +#define AUD_OCRAM_LPCG 0x59590000 +#define AUD_EDMA_0_LPCG 0x595f0000 +#define AUD_ASRC_1_LPCG 0x59c00000 +#define AUD_ESAI_1_LPCG 0x59c10000 +#define AUD_SAI_6_LPCG 0x59c20000 +#define AUD_SAI_7_LPCG 0x59c30000 +#define AUD_AMIX_LPCG 0x59c40000 +#define AUD_MQS_LPCG 0x59c50000 +#define AUD_ACM_LPCG 0x59c60000 +#define AUD_REC_CLK0_LPCG 0x59d00000 +#define AUD_REC_CLK1_LPCG 0x59d10000 +#define AUD_PLL_CLK0_LPCG 0x59d20000 +#define AUD_PLL_CLK1_LPCG 0x59d30000 +#define AUD_MCLKOUT0_LPCG 0x59d50000 +#define AUD_MCLKOUT1_LPCG 0x59d60000 +#define AUD_EDMA_1_LPCG 0x59df0000 + + +/* Connectivity SS */ +#define USDHC_0_LPCG 0x5B200000 +#define USDHC_1_LPCG 0x5B210000 +#define USDHC_2_LPCG 0x5B220000 +#define ENET_0_LPCG 0x5B230000 +#define ENET_1_LPCG 0x5B240000 +#define DTCP_LPCG 0x5B250000 +#define MLB_LPCG 0x5B260000 +#define USB_2_LPCG 0x5B270000 +#define USB_3_LPCG 0x5B280000 +#define NAND_LPCG 0x5B290000 +#define EDMA_LPCG 0x5B2A0000 + +/* CM40 SS */ +#define CM40_I2C_LPCG 0x37630000 + +/* CM41 SS */ +#define CM41_I2C_LPCG 0x3B630000 + +#endif diff --git a/arch/arm/include/asm/arch-imx8/imx8qxp_lpcg.h b/arch/arm/include/asm/arch-imx8/imx8qxp_lpcg.h new file mode 100644 index 0000000..5fed514 --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/imx8qxp_lpcg.h @@ -0,0 +1,195 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SC_LPCG_H +#define _SC_LPCG_H + +/*LSIO SS */ +#define PWM_0_LPCG 0x5D400000 +#define PWM_1_LPCG 0x5D410000 +#define PWM_2_LPCG 0x5D420000 +#define PWM_3_LPCG 0x5D430000 +#define PWM_4_LPCG 0x5D440000 +#define PWM_5_LPCG 0x5D450000 +#define PWM_6_LPCG 0x5D460000 +#define PWM_7_LPCG 0x5D470000 +#define GPIO_0_LPCG 0x5D480000 +#define GPIO_1_LPCG 0x5D490000 +#define GPIO_2_LPCG 0x5D4A0000 +#define GPIO_3_LPCG 0x5D4B0000 +#define GPIO_4_LPCG 0x5D4C0000 +#define GPIO_5_LPCG 0x5D4D0000 +#define GPIO_6_LPCG 0x5D4E0000 +#define GPIO_7_LPCG 0x5D4F0000 +#define FSPI_0_LPCG 0x5D520000 +#define FSPI_1_LPCG 0x5D530000 +#define GPT_0_LPCG 0x5D540000 +#define GPT_1_LPCG 0x5D550000 +#define GPT_2_LPCG 0x5D560000 +#define GPT_3_LPCG 0x5D570000 +#define GPT_4_LPCG 0x5D580000 +#define OCRAM_LPCG 0x5D590000 +#define KPP_LPCG 0x5D5A0000 +#define ROMCP_LPCG 0x5D500000 +#define MU_5A_LPCG 0x5D600000 +#define MU_6A_LPCG 0x5D610000 +#define MU_7A_LPCG 0x5D620000 +#define MU_8A_LPCG 0x5D630000 +#define MU_9A_LPCG 0x5D640000 +#define MU_10A_LPCG 0x5D650000 +#define MU_11A_LPCG 0x5D660000 +#define MU_12A_LPCG 0x5D670000 +#define MU_13A_LPCG 0x5D680000 + +/* HSIO SS */ +#define CRR_5_LPCG 0x5F0F0000 +#define CRR_4_LPCG 0x5F0E0000 +#define CRR_3_LPCG 0x5F0D0000 +#define CRR_2_LPCG 0x5F0C0000 +#define CRR_1_LPCG 0x5F0B0000 +#define CRR_0_LPCG 0x5F0A0000 +#define PHY_1_LPCG 0x5F090000 +#define PHY_2_LPCG 0x5F080000 +#define SATA_0_LPCG 0x5F070000 +#define PCIE_B_LPCG 0x5F060000 +#define PCIE_A_LPCG 0x5F050000 + +/* DMA SS */ +#define FLEX_CAN_2_LPCG 0x5ACF0000 +#define FLEX_CAN_1_LPCG 0x5ACE0000 +#define FLEX_CAN_0_LPCG 0x5ACD0000 +#define FTM_1_LPCG 0x5ACB0000 +#define FTM_0_LPCG 0x5ACA0000 +#define ADC_0_LPCG 0x5AC80000 +#define LPI2C_3_LPCG 0x5AC30000 +#define LPI2C_2_LPCG 0x5AC20000 +#define LPI2C_1_LPCG 0x5AC10000 +#define LPI2C_0_LPCG 0x5AC00000 +#define PWM_LPCG 0x5A590000 +#define LCD_LPCG 0x5A580000 +#define LPUART_3_LPCG 0x5A490000 +#define LPUART_2_LPCG 0x5A480000 +#define LPUART_1_LPCG 0x5A470000 +#define LPUART_0_LPCG 0x5A460000 +#define LPSPI_3_LPCG 0x5A430000 +#define LPSPI_2_LPCG 0x5A420000 +#define LPSPI_1_LPCG 0x5A410000 +#define LPSPI_0_LPCG 0x5A400000 + +/* Display SS */ +#define DC_0_LPCG 0x56010000 +#define DC_1_LPCG 0x57010000 + +/* LVDS */ +#define DI_LVDS_0_LPCG 0x56243000 +#define DI_LVDS_1_LPCG 0x57243000 + +/* DI HDMI */ +#define DI_HDMI_LPCG 0x56263000 + +/* RX-HDMI */ +#define RX_HDMI_LPCG 0x58263000 + +/* MIPI CSI SS */ +#define MIPI_CSI_0_LPCG 0x58223000 +#define MIPI_CSI_1_LPCG 0x58243000 + +/* PARALLEL CSI SS */ +#define PARALLEL_CSI_LPCG 0x58263000 + +/* Display MIPI SS */ +#define DI_MIPI0_LPCG 0x56223000 +#define DI_MIPI1_LPCG 0x56243000 + +/* Imaging SS */ +#define IMG_JPEG_ENC_LPCG 0x585F0000 +#define IMG_JPEG_DEC_LPCG 0x585D0000 +#define IMG_PXL_LINK_DC1_LPCG 0x585C0000 +#define IMG_PXL_LINK_DC0_LPCG 0x585B0000 +#define IMG_PXL_LINK_HDMI_LPCG 0x585A0000 +#define IMG_PXL_LINK_CSI1_LPCG 0x58590000 +#define IMG_PXL_LINK_CSI0_LPCG 0x58580000 +#define IMG_PDMA_7_LPCG 0x58570000 +#define IMG_PDMA_6_LPCG 0x58560000 +#define IMG_PDMA_5_LPCG 0x58550000 +#define IMG_PDMA_4_LPCG 0x58540000 +#define IMG_PDMA_3_LPCG 0x58530000 +#define IMG_PDMA_2_LPCG 0x58520000 +#define IMG_PDMA_1_LPCG 0x58510000 +#define IMG_PDMA_0_LPCG 0x58500000 + +/* HSIO SS */ +#define HSIO_GPIO_LPCG 0x5F100000 +#define HSIO_MISC_LPCG 0x5F0F0000 +#define HSIO_SATA_CRR4_LPCG 0x5F0E0000 +#define HSIO_PCIE_X1_CRR3_LPCG 0x5F0D0000 +#define HSIO_PCIE_X2_CRR2_LPCG 0x5F0C0000 +#define HSIO_PHY_X1_CRR1_LPCG 0x5F0B0000 +#define HSIO_PHY_X2_CRR0_LPCG 0x5F0A0000 +#define HSIO_PHY_X1_LPCG 0x5F090000 +#define HSIO_PHY_X2_LPCG 0x5F080000 +#define HSIO_SATA_LPCG 0x5F070000 +#define HSIO_PCIE_X1_LPCG 0x5F060000 +#define HSIO_PCIE_X2_LPCG 0x5F050000 + +/* M4 SS */ +#define M4_0_I2C_LPCG 0x37630000 +#define M4_0_LPUART_LPCG 0x37620000 +#define M4_0_LPIT_LPCG 0x37610000 +#define M4_1_I2C_LPCG 0x3B630000 +#define M4_1_LPUART_LPCG 0x3B620000 +#define M4_1_LPIT_LPCG 0x3B610000 + +/* Audio SS */ +#define AUD_ASRC_0_LPCG 0x59400000 +#define AUD_ESAI_0_LPCG 0x59410000 +#define AUD_SPDIF_0_LPCG 0x59420000 +#define AUD_SAI_0_LPCG 0x59440000 +#define AUD_SAI_1_LPCG 0x59450000 +#define AUD_SAI_2_LPCG 0x59460000 +#define AUD_SAI_3_LPCG 0x59470000 +#define AUD_GPT_5_LPCG 0x594B0000 +#define AUD_GPT_6_LPCG 0x594C0000 +#define AUD_GPT_7_LPCG 0x594D0000 +#define AUD_GPT_8_LPCG 0x594E0000 +#define AUD_GPT_9_LPCG 0x594F0000 +#define AUD_GPT_10_LPCG 0x59500000 +#define AUD_DSP_LPCG 0x59580000 +#define AUD_OCRAM_LPCG 0x59590000 +#define AUD_EDMA_0_LPCG 0x595f0000 +#define AUD_ASRC_1_LPCG 0x59c00000 +#define AUD_SAI_4_LPCG 0x59c20000 +#define AUD_SAI_5_LPCG 0x59c30000 +#define AUD_AMIX_LPCG 0x59c40000 +#define AUD_MQS_LPCG 0x59c50000 +#define AUD_ACM_LPCG 0x59c60000 +#define AUD_REC_CLK0_LPCG 0x59d00000 +#define AUD_REC_CLK1_LPCG 0x59d10000 +#define AUD_PLL_CLK0_LPCG 0x59d20000 +#define AUD_PLL_CLK1_LPCG 0x59d30000 +#define AUD_MCLKOUT0_LPCG 0x59d50000 +#define AUD_MCLKOUT1_LPCG 0x59d60000 +#define AUD_EDMA_1_LPCG 0x59df0000 + + +/* Connectivity SS */ +#define USDHC_0_LPCG 0x5B200000 +#define USDHC_1_LPCG 0x5B210000 +#define USDHC_2_LPCG 0x5B220000 +#define ENET_0_LPCG 0x5B230000 +#define ENET_1_LPCG 0x5B240000 +#define DTCP_LPCG 0x5B250000 +#define MLB_LPCG 0x5B260000 +#define USB_2_LPCG 0x5B270000 +#define USB_3_LPCG 0x5B280000 +#define NAND_LPCG 0x5B290000 +#define EDMA_LPCG 0x5B2A0000 + +/* CM40 SS */ +#define CM40_I2C_LPCG 0x37630000 + + +#endif diff --git a/arch/arm/include/asm/arch-imx8/lpcg.h b/arch/arm/include/asm/arch-imx8/lpcg.h new file mode 100644 index 0000000..b3a4545 --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/lpcg.h @@ -0,0 +1,26 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_IMX8_LPCG_H__ +#define __ASM_ARCH_IMX8_LPCG_H__ + +#if defined(CONFIG_IMX8QM) +#include "imx8qm_lpcg.h" +#elif defined(CONFIG_IMX8QXP) +#include "imx8qxp_lpcg.h" +#else +#error "No lpcg header" +#endif + +void lpcg_clock_off(u32 lpcg_addr, u8 clk); +void lpcg_clock_on(u32 lpcg_addr, u8 clk); +void lpcg_clock_autogate(u32 lpcg_addr, u8 clk); +bool lpcg_is_clock_on(u32 lpcg_addr, u8 clk); +void lpcg_all_clock_off(u32 lpcg_addr); +void lpcg_all_clock_on(u32 lpcg_addr); +void lpcg_all_clock_autogate(u32 lpcg_addr); + +#endif /* __ASM_ARCH_IMX8_LPCG_H__ */ diff --git a/arch/arm/mach-imx/imx8/Makefile b/arch/arm/mach-imx/imx8/Makefile index 31ad169..e23f84f 100644 --- a/arch/arm/mach-imx/imx8/Makefile +++ b/arch/arm/mach-imx/imx8/Makefile @@ -4,4 +4,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += cpu.o iomux.o +obj-y += cpu.o iomux.o lpcg.o diff --git a/arch/arm/mach-imx/imx8/lpcg.c b/arch/arm/mach-imx/imx8/lpcg.c new file mode 100644 index 0000000..5f5d770 --- /dev/null +++ b/arch/arm/mach-imx/imx8/lpcg.c @@ -0,0 +1,115 @@ +/* + * Copyright 2017-2019 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +#define LPCG_CLOCK_MASK 0x3U +#define LPCG_CLOCK_OFF 0x0U +#define LPCG_CLOCK_ON 0x2U +#define LPCG_CLOCK_AUTO 0x3U +#define LPCG_CLOCK_STOP 0x8U + +#define LPCG_ALL_CLOCK_OFF 0x00000000U +#define LPCG_ALL_CLOCK_ON 0x22222222U +#define LPCG_ALL_CLOCK_AUTO 0x33333333U +#define LPCG_ALL_CLOCK_STOP 0x88888888U + +static inline void lpcg_write(u32 lpcgVal, ulong lpcg_addr) +{ + /* + * Write twice with 4x DSC clock cycles (40x IPS clock cycles) interval + * to work around LPCG issue + */ + writel(lpcgVal, lpcg_addr); + udelay(10); /* 10us is enough. Worst case is 40x IPS cycle (200Mhz) */ + writel(lpcgVal, lpcg_addr); + udelay(10); +} + +void lpcg_clock_off(u32 lpcg_addr, u8 clk) +{ + u32 lpcgVal; + + /* Read from LPCG */ + lpcgVal = readl((ulong)lpcg_addr); + + /* Modify */ + lpcgVal &= ~((u32)(LPCG_CLOCK_MASK) << (clk * 4U)); + lpcgVal |= ((u32)(LPCG_CLOCK_OFF) << (clk * 4U)); + + /* Write to LPCG */ + lpcg_write(lpcgVal, (ulong)lpcg_addr); +} + +void lpcg_clock_on(u32 lpcg_addr, u8 clk) +{ + u32 lpcgVal; + + /* Read from LPCG */ + lpcgVal = readl((ulong)lpcg_addr); + + /* Modify */ + lpcgVal &= ~((u32)(LPCG_CLOCK_MASK) << (clk * 4U)); + lpcgVal |= ((u32)(LPCG_CLOCK_ON) << (clk * 4U)); + + /* Write to LPCG */ + lpcg_write(lpcgVal, (ulong)lpcg_addr); +} + +bool lpcg_is_clock_on(u32 lpcg_addr, u8 clk) +{ + u32 lpcgVal; + + /* Read from LPCG */ + lpcgVal = readl((ulong)lpcg_addr); + lpcgVal = (lpcgVal >> (clk * 4U)) & (u32)(LPCG_CLOCK_MASK); + + if (lpcgVal == LPCG_CLOCK_ON) + return true; + + return false; +} + +void lpcg_clock_autogate(u32 lpcg_addr, u8 clk) +{ + u32 lpcgVal; + + /* Read from LPCG */ + lpcgVal = readl((ulong)lpcg_addr); + + /* Modify */ + lpcgVal &= ~((u32)(LPCG_CLOCK_MASK) << (clk * 4U)); + lpcgVal |= ((u32)(LPCG_CLOCK_AUTO) << (clk * 4U)); + + /* Write to LPCG */ + lpcg_write(lpcgVal, (ulong)lpcg_addr); +} + +void lpcg_all_clock_off(u32 lpcg_addr) +{ + /* Write to LPCG */ + lpcg_write(LPCG_ALL_CLOCK_OFF, (ulong)lpcg_addr); +} + +void lpcg_all_clock_on(u32 lpcg_addr) +{ + /* Write to LPCG */ + lpcg_write(LPCG_ALL_CLOCK_ON, (ulong)lpcg_addr); + + /* Wait for clocks to start */ + while ((readl((ulong)lpcg_addr) & LPCG_ALL_CLOCK_STOP) != 0U) + { + } +} + +void lpcg_all_clock_autogate(u32 lpcg_addr) +{ + /* Write to LPCG */ + lpcg_write(LPCG_ALL_CLOCK_AUTO, (ulong)lpcg_addr); +}