From patchwork Wed Aug 31 15:55:31 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 112600 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 9A5B7B6F72 for ; Thu, 1 Sep 2011 01:56:35 +1000 (EST) Received: from localhost ([::1]:48272 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Qyn9U-0000s9-RW for incoming@patchwork.ozlabs.org; Wed, 31 Aug 2011 11:56:32 -0400 Received: from eggs.gnu.org ([140.186.70.92]:54808) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Qyn9O-0000rD-6P for qemu-devel@nongnu.org; Wed, 31 Aug 2011 11:56:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Qyn9M-0005dh-UZ for qemu-devel@nongnu.org; Wed, 31 Aug 2011 11:56:26 -0400 Received: from mnementh.archaic.org.uk ([81.2.115.146]:38264) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Qyn9M-0005da-E3 for qemu-devel@nongnu.org; Wed, 31 Aug 2011 11:56:24 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1Qyn8W-0008Qs-6d; Wed, 31 Aug 2011 16:55:32 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Wed, 31 Aug 2011 16:55:31 +0100 Message-Id: <1314806132-32389-2-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1314806132-32389-1-git-send-email-peter.maydell@linaro.org> References: <1314806132-32389-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 81.2.115.146 Cc: =?UTF-8?q?Juha=20Riihim=C3=A4ki?= , Riku Voipio , patches@linaro.org Subject: [Qemu-devel] [PATCH 1/2] omap_intc: Use MemoryRegion API X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Convert omap_intc to use the MemoryRegion API Signed-off-by: Peter Maydell --- hw/omap_intc.c | 64 ++++++++++++++++++++++++++----------------------------- 1 files changed, 30 insertions(+), 34 deletions(-) diff --git a/hw/omap_intc.c b/hw/omap_intc.c index f1f570e..38637c6 100644 --- a/hw/omap_intc.c +++ b/hw/omap_intc.c @@ -19,6 +19,7 @@ */ #include "hw.h" #include "omap.h" +#include "exec-memory.h" /* Interrupt Handlers */ struct omap_intr_handler_bank_s { @@ -34,6 +35,7 @@ struct omap_intr_handler_bank_s { struct omap_intr_handler_s { qemu_irq *pins; qemu_irq parent_intr[2]; + MemoryRegion mmio; unsigned char nbanks; int level_only; @@ -142,7 +144,8 @@ static void omap_set_intr_noedge(void *opaque, int irq, int req) bank->irqs = (bank->inputs &= ~(1 << n)) | bank->swi; } -static uint32_t omap_inth_read(void *opaque, target_phys_addr_t addr) +static uint64_t omap_inth_read(void *opaque, target_phys_addr_t addr, + unsigned size) { struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque; int i, offset = addr; @@ -220,7 +223,7 @@ static uint32_t omap_inth_read(void *opaque, target_phys_addr_t addr) } static void omap_inth_write(void *opaque, target_phys_addr_t addr, - uint32_t value) + uint64_t value, unsigned size) { struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque; int i, offset = addr; @@ -312,16 +315,14 @@ static void omap_inth_write(void *opaque, target_phys_addr_t addr, OMAP_BAD_REG(addr); } -static CPUReadMemoryFunc * const omap_inth_readfn[] = { - omap_badwidth_read32, - omap_badwidth_read32, - omap_inth_read, -}; - -static CPUWriteMemoryFunc * const omap_inth_writefn[] = { - omap_inth_write, - omap_inth_write, - omap_inth_write, +static const MemoryRegionOps omap_inth_mem_ops = { + .read = omap_inth_read, + .write = omap_inth_write, + .endianness = DEVICE_NATIVE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4, + }, }; void omap_inth_reset(struct omap_intr_handler_s *s) @@ -356,7 +357,6 @@ struct omap_intr_handler_s *omap_inth_init(target_phys_addr_t base, unsigned long size, unsigned char nbanks, qemu_irq **pins, qemu_irq parent_irq, qemu_irq parent_fiq, omap_clk clk) { - int iomemtype; struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) g_malloc0(sizeof(struct omap_intr_handler_s) + sizeof(struct omap_intr_handler_bank_s) * nbanks); @@ -368,16 +368,16 @@ struct omap_intr_handler_s *omap_inth_init(target_phys_addr_t base, if (pins) *pins = s->pins; - omap_inth_reset(s); + memory_region_init_io(&s->mmio, &omap_inth_mem_ops, s, "omap-intc", size); + memory_region_add_subregion(get_system_memory(), base, &s->mmio); - iomemtype = cpu_register_io_memory(omap_inth_readfn, - omap_inth_writefn, s, DEVICE_NATIVE_ENDIAN); - cpu_register_physical_memory(base, size, iomemtype); + omap_inth_reset(s); return s; } -static uint32_t omap2_inth_read(void *opaque, target_phys_addr_t addr) +static uint64_t omap2_inth_read(void *opaque, target_phys_addr_t addr, + unsigned size) { struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque; int offset = addr; @@ -455,7 +455,7 @@ static uint32_t omap2_inth_read(void *opaque, target_phys_addr_t addr) } static void omap2_inth_write(void *opaque, target_phys_addr_t addr, - uint32_t value) + uint64_t value, unsigned size) { struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque; int offset = addr; @@ -558,16 +558,14 @@ static void omap2_inth_write(void *opaque, target_phys_addr_t addr, OMAP_BAD_REG(addr); } -static CPUReadMemoryFunc * const omap2_inth_readfn[] = { - omap_badwidth_read32, - omap_badwidth_read32, - omap2_inth_read, -}; - -static CPUWriteMemoryFunc * const omap2_inth_writefn[] = { - omap2_inth_write, - omap2_inth_write, - omap2_inth_write, +static const MemoryRegionOps omap2_inth_mem_ops = { + .read = omap2_inth_read, + .write = omap2_inth_write, + .endianness = DEVICE_NATIVE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4, + }, }; struct omap_intr_handler_s *omap2_inth_init(target_phys_addr_t base, @@ -575,7 +573,6 @@ struct omap_intr_handler_s *omap2_inth_init(target_phys_addr_t base, qemu_irq parent_irq, qemu_irq parent_fiq, omap_clk fclk, omap_clk iclk) { - int iomemtype; struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) g_malloc0(sizeof(struct omap_intr_handler_s) + sizeof(struct omap_intr_handler_bank_s) * nbanks); @@ -588,11 +585,10 @@ struct omap_intr_handler_s *omap2_inth_init(target_phys_addr_t base, if (pins) *pins = s->pins; - omap_inth_reset(s); + memory_region_init_io(&s->mmio, &omap2_inth_mem_ops, s, "omap2-intc", size); + memory_region_add_subregion(get_system_memory(), base, &s->mmio); - iomemtype = cpu_register_io_memory(omap2_inth_readfn, - omap2_inth_writefn, s, DEVICE_NATIVE_ENDIAN); - cpu_register_physical_memory(base, size, iomemtype); + omap_inth_reset(s); return s; }