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[1/2] i2c: i801: Fix PCI ID sorting

Message ID 20190701131534.19537-1-jarkko.nikula@linux.intel.com
State Accepted
Headers show
Series [1/2] i2c: i801: Fix PCI ID sorting | expand

Commit Message

Jarkko Nikula July 1, 2019, 1:15 p.m. UTC
I managed to break sorting in PCI ID defines in my last two patches:

commit 5cd1c56c42be ("i2c: i801: Add support for Intel Comet Lake")
commit 9be1485accd4 ("i2c: i801: Add support for Intel Elkhart Lake")

Fix them up.

Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
---
 drivers/i2c/busses/i2c-i801.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Comments

Jean Delvare July 4, 2019, 9:40 a.m. UTC | #1
On Mon, 1 Jul 2019 16:15:33 +0300, Jarkko Nikula wrote:
> I managed to break sorting in PCI ID defines in my last two patches:

Omg this is so bad. Let me fetch my whip ;-)

> commit 5cd1c56c42be ("i2c: i801: Add support for Intel Comet Lake")
> commit 9be1485accd4 ("i2c: i801: Add support for Intel Elkhart Lake")
> 
> Fix them up.
>
> Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
> ---
>  drivers/i2c/busses/i2c-i801.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> (...)

Reviewed-by: Jean Delvare <jdelvare@suse.de>
Wolfram Sang July 5, 2019, 6:30 p.m. UTC | #2
On Mon, Jul 01, 2019 at 04:15:33PM +0300, Jarkko Nikula wrote:
> I managed to break sorting in PCI ID defines in my last two patches:
> 
> commit 5cd1c56c42be ("i2c: i801: Add support for Intel Comet Lake")
> commit 9be1485accd4 ("i2c: i801: Add support for Intel Elkhart Lake")
> 
> Fix them up.
> 
> Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>

Applied to for-next, thanks!
diff mbox series

Patch

diff --git a/drivers/i2c/busses/i2c-i801.c b/drivers/i2c/busses/i2c-i801.c
index 1e7f6ae62b4c..1ddbfe3bb745 100644
--- a/drivers/i2c/busses/i2c-i801.c
+++ b/drivers/i2c/busses/i2c-i801.c
@@ -203,6 +203,7 @@ 
 				 STATUS_ERROR_FLAGS)
 
 /* Older devices have their ID defined in <linux/pci_ids.h> */
+#define PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS		0x02a3
 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS		0x0f12
 #define PCI_DEVICE_ID_INTEL_CDF_SMBUS			0x18df
 #define PCI_DEVICE_ID_INTEL_DNV_SMBUS			0x19df
@@ -220,6 +221,7 @@ 
 #define PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS		0x31d4
 #define PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS		0x34a3
 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS		0x3b30
+#define PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS		0x4b23
 #define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS		0x5ad4
 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS		0x8c22
 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS		0x8ca2
@@ -236,8 +238,6 @@ 
 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS	0xa223
 #define PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS	0xa2a3
 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS		0xa323
-#define PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS		0x02a3
-#define PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS		0x4b23
 
 struct i801_mux_config {
 	char *gpio_chip;