diff mbox series

[v2,1/2] dt-bindings: clock: cdce925: Add regulator documentation

Message ID 1561691950-42154-2-git-send-email-preid@electromag.com.au
State Not Applicable, archived
Headers show
Series clk: clk-cdce925: Add regulator support | expand

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Commit Message

Phil Reid June 28, 2019, 3:19 a.m. UTC
The cdce925 has two separate supply pins. Document the bindings
for them.

Signed-off-by: Phil Reid <preid@electromag.com.au>
---
 Documentation/devicetree/bindings/clock/ti,cdce925.txt | 4 ++++
 1 file changed, 4 insertions(+)

Comments

Rob Herring July 22, 2019, 6:18 p.m. UTC | #1
On Fri, 28 Jun 2019 11:19:09 +0800, Phil Reid wrote:
> The cdce925 has two separate supply pins. Document the bindings
> for them.
> 
> Signed-off-by: Phil Reid <preid@electromag.com.au>
> ---
>  Documentation/devicetree/bindings/clock/ti,cdce925.txt | 4 ++++
>  1 file changed, 4 insertions(+)
> 

Reviewed-by: Rob Herring <robh@kernel.org>
Stephen Boyd Sept. 6, 2019, 5:32 p.m. UTC | #2
Quoting Phil Reid (2019-06-27 20:19:09)
> The cdce925 has two separate supply pins. Document the bindings
> for them.
> 
> Signed-off-by: Phil Reid <preid@electromag.com.au>
> ---

Applied to clk-next
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/clock/ti,cdce925.txt b/Documentation/devicetree/bindings/clock/ti,cdce925.txt
index 0d01f2d..26544c8 100644
--- a/Documentation/devicetree/bindings/clock/ti,cdce925.txt
+++ b/Documentation/devicetree/bindings/clock/ti,cdce925.txt
@@ -24,6 +24,8 @@  Required properties:
 Optional properties:
  - xtal-load-pf: Crystal load-capacitor value to fine-tune performance on a
                  board, or to compensate for external influences.
+- vdd-supply: A regulator node for Vdd
+- vddout-supply: A regulator node for Vddout
 
 For all PLL1, PLL2, ... an optional child node can be used to specify spread
 spectrum clocking parameters for a board.
@@ -41,6 +43,8 @@  Example:
 		clocks = <&xtal_27Mhz>;
 		#clock-cells = <1>;
 		xtal-load-pf = <5>;
+		vdd-supply = <&1v8-reg>;
+		vddout-supply = <&3v3-reg>;
 		/* PLL options to get SSC 1% centered */
 		PLL2 {
 			spread-spectrum = <4>;