| Message ID | 20190627164900.GA11074@ibm-toto.the-meissners.org |
|---|---|
| State | New |
| Headers | show |
| Series | , PR Fix floatsi{sf,df}2 and floatunssi{sf,df}2 for a future powerpc machine | expand |
Hi Mike, On Thu, Jun 27, 2019 at 12:49:00PM -0400, Michael Meissner wrote: > As I detail in PR 91009, I had some testsuite failures with my patches for a > future machine. In the future patches, I added new RTL attributes to support > the new prefixed load/store instructions (which will include pc-relative > support). This new attribute needs to look at the 'type' RTL attribute, and > that in turn depends on doing a constrain operands to determine whether the > insn is a load, store, or add instruction. > > This constrain operands call occurs before the first split pass. The insns > that convert SImode to SFmode or DFmode which are split in the first pass, > currently use the "wa" constraint for the floating point result. Unfortunately > if the user uses the -mno-vsx option, the "wa" constraint becomes NO_REGS. Yes, constrain_operands is called very early. It's called during combine for pretty much all insns, but it's already called by ifcvt ("ce1", the eighth or so RTL pass) for some. Instruction costing needs to figure out which instruction alternatives are enabled, and which not. > This patch is a rather limited patch that just adds an alternative using the > "d" constraint, so there is a valid alternative before splitting. The "before splitting" isn't really relevant: you have to have some alternative enabled for all insns you generate. Because lfiwax (the machine instruction after which this pattern is named) only works on floating point registers, not all VSX registers, and this pattern is generated from places that do not check if VSX is enabled, adding a "d" alternative sounds good yes. > This patch does not do the cleanup mentioned in PR 90822. That will still be > done, but I wanted to fix the actual problem before doing the next iteration of > the code cleanup. > > I have done a bootstrap and make check, and there were no regressions. Can I > check this into the trunk? [ Please mention on what kind of system, what configuration. This matters when things go wrong. Something like "powerpc64le-linux, power8" is enough info usually, if you used default configurations. ] > 2019-06-27 Michael Meissner <meissner@linux.ibm.com> > > PR target/91009 > * config/rs6000/rs6000.md (floatsi<mode>2_lfiwax): Add non-VSX > alternative. > (floatsi<mode>2_lfiwax_mem): Add non-VSX alternative. > (floatunssi<mode>2_lfiwzx): Add non-VSX alternative. > (floatunssi<mode>2_lfiwzx_mem): Add non-VSX alternative. The patch is fine for trunk. Thanks Mike. Segher
Index: gcc/config/rs6000/rs6000.md =================================================================== --- gcc/config/rs6000/rs6000.md (revision 272436) +++ gcc/config/rs6000/rs6000.md (working copy) @@ -5227,9 +5227,9 @@ (define_insn "lfiwax" ; not be needed and also in case the insns are deleted as dead code. (define_insn_and_split "floatsi<mode>2_lfiwax" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Fv>") - (float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r"))) - (clobber (match_scratch:DI 2 "=wa"))] + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<Fv>") + (float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r,r"))) + (clobber (match_scratch:DI 2 "=d,wa"))] "TARGET_HARD_FLOAT && TARGET_LFIWAX && <SI_CONVERT_FP> && can_create_pseudo_p ()" "#" @@ -5266,11 +5266,11 @@ (define_insn_and_split "floatsi<mode>2_l (set_attr "type" "fpload")]) (define_insn_and_split "floatsi<mode>2_lfiwax_mem" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Fv>") + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<Fv>") (float:SFDF (sign_extend:DI - (match_operand:SI 1 "indexed_or_indirect_operand" "Z")))) - (clobber (match_scratch:DI 2 "=wa"))] + (match_operand:SI 1 "indexed_or_indirect_operand" "Z,Z")))) + (clobber (match_scratch:DI 2 "=d,wa"))] "TARGET_HARD_FLOAT && TARGET_LFIWAX && <SI_CONVERT_FP>" "#" "" @@ -5303,9 +5303,9 @@ (define_insn "lfiwzx" (set_attr "isa" "*,p8v,p8v,p9v")]) (define_insn_and_split "floatunssi<mode>2_lfiwzx" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Fv>") - (unsigned_float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r"))) - (clobber (match_scratch:DI 2 "=wa"))] + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<Fv>") + (unsigned_float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r,r"))) + (clobber (match_scratch:DI 2 "=d,wa"))] "TARGET_HARD_FLOAT && TARGET_LFIWZX && <SI_CONVERT_FP>" "#" "" @@ -5341,11 +5341,11 @@ (define_insn_and_split "floatunssi<mode> (set_attr "type" "fpload")]) (define_insn_and_split "floatunssi<mode>2_lfiwzx_mem" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Fv>") + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<Fv>") (unsigned_float:SFDF (zero_extend:DI - (match_operand:SI 1 "indexed_or_indirect_operand" "Z")))) - (clobber (match_scratch:DI 2 "=wa"))] + (match_operand:SI 1 "indexed_or_indirect_operand" "Z,Z")))) + (clobber (match_scratch:DI 2 "=d,wa"))] "TARGET_HARD_FLOAT && TARGET_LFIWZX && <SI_CONVERT_FP>" "#" ""