x86: fix CVT{,T}PD2PI insns
diff mbox series

Message ID 5D14866E020000780023B753@prv1-mh.provo.novell.com
State New
Headers show
Series
  • x86: fix CVT{,T}PD2PI insns
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Commit Message

Jan Beulich June 27, 2019, 9:03 a.m. UTC
With just an "m" constraint misaligned memory operands won't be forced
into a register, and hence cause #GP. So far this was guaranteed only
in the case that CVT{,T}PD2DQ were chosen (which looks to be the case on
x86-64 only).

Instead of switching the second alternative to Bm, use just m on the
first and replace nonimmediate_operand by vector_operand.

gcc/
2019-06-27  Jan Beulich  <jbeulich@suse.com>

	* config/i386/sse.md (sse2_cvtpd2pi, sse2_cvttpd2pi): Use
	vector_operand plus "m" constraint.

gcc/testsuite/
2019-06-27  Jan Beulich  <jbeulich@suse.com>

	* gcc.target/i386/cvtpd2pi: New.

Patch
diff mbox series

--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -5505,7 +5505,7 @@ 
 
 (define_insn "sse2_cvtpd2pi"
   [(set (match_operand:V2SI 0 "register_operand" "=v,?!y")
-	(unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand" "vBm,xm")]
+	(unspec:V2SI [(match_operand:V2DF 1 "vector_operand" "vm,xm")]
 		     UNSPEC_FIX_NOTRUNC))]
   "TARGET_SSE2"
   "@
@@ -5523,7 +5523,7 @@ 
 
 (define_insn "sse2_cvttpd2pi"
   [(set (match_operand:V2SI 0 "register_operand" "=v,?!y")
-	(fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" "vBm,xm")))]
+	(fix:V2SI (match_operand:V2DF 1 "vector_operand" "vm,xm")))]
   "TARGET_SSE2"
   "@
    * return TARGET_AVX ? \"vcvttpd2dq{x}\t{%1, %0|%0, %1}\" : \"cvttpd2dq\t{%1, %0|%0, %1}\";
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/cvtpd2pi.c
@@ -0,0 +1,36 @@ 
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2" } */
+
+typedef int __attribute__((vector_size(8))) v2si_t;
+typedef int __attribute__((vector_size(16))) v4si_t;
+typedef double __attribute__((vector_size(16))) v2df_t;
+
+struct __attribute__((packed)) s {
+  int i;
+  v2si_t m;
+  v4si_t v;
+};
+
+int test (struct s*ps)
+{
+  v4si_t r = ps->v;
+  v2si_t m;
+
+  if (ps->i > 0)
+    {
+      asm volatile ("" : "+m" (*ps));
+      m = __builtin_ia32_cvtpd2pi ((v2df_t)ps->v);
+      r[0] = __builtin_ia32_paddd (m, m)[0];
+    }
+  else
+    {
+      asm volatile ("" : "+m" (*ps));
+      m = __builtin_ia32_cvttpd2pi ((v2df_t)ps->v);
+      r[0] = __builtin_ia32_paddd (m, m)[0];
+    }
+
+  return r[0];
+}
+
+/* { dg-final { scan-assembler-not "cvtpd2pi\[ \t]\[^\n\r]*\\(" } } */
+/* { dg-final { scan-assembler-not "cvttpd2pi\[ \t]\[^\n\r]*\\(" } } */