| Message ID | 20190626221935.23477-2-marex@denx.de |
|---|---|
| State | Accepted, archived |
| Commit | 4a9f633e3d13dbeb6a88de13074c48ec63210f5c |
| Delegated to: | Simon Goldschmidt |
| Headers | show |
| Series | [U-Boot,1/5] ARM: socfpga: vining_fpga: Rename VINING|FPGA | expand |
On Thu, Jun 27, 2019 at 12:21 AM Marek Vasut <marex@denx.de> wrote: > > Pick minor changes from the downstream DT, disable MMC, add GMAC0 node > and adjust PHY skew settings for GMAC1. > > Signed-off-by: Marek Vasut <marex@denx.de> > Cc: Silvio Fricke <silvio.fricke@softing.com> > Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> > --- > .../dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi | 2 +- > arch/arm/dts/socfpga_cyclone5_vining_fpga.dts | 15 ++++++++++++--- > 2 files changed, 13 insertions(+), 4 deletions(-) > > diff --git a/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi > index db55a4ecad..44bedd8b67 100644 > --- a/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi > +++ b/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi > @@ -20,7 +20,7 @@ > }; > > &mmc { > - u-boot,dm-pre-reloc; > + status = "disabled"; > }; > > &qspi { > diff --git a/arch/arm/dts/socfpga_cyclone5_vining_fpga.dts b/arch/arm/dts/socfpga_cyclone5_vining_fpga.dts > index be52fbf43d..3fb6e14372 100644 > --- a/arch/arm/dts/socfpga_cyclone5_vining_fpga.dts > +++ b/arch/arm/dts/socfpga_cyclone5_vining_fpga.dts > @@ -1,6 +1,6 @@ > // SPDX-License-Identifier: (GPL-2.0+ OR X11) > /* > - * Copyright (C) 2015 Marek Vasut <marex@denx.de> > + * Copyright (C) 2015-2019 Marek Vasut <marex@denx.de> > */ > > #include "socfpga_cyclone5.dtsi" > @@ -65,6 +65,11 @@ > }; > }; > > +&gmac0 { > + status = "disabled"; > + phy-mode = "gmii"; > +}; > + > &gmac1 { > status = "okay"; > phy-mode = "rgmii"; > @@ -84,10 +89,14 @@ > rxd1-skew-ps = <0>; > rxd2-skew-ps = <0>; > rxd3-skew-ps = <0>; > + txd0-skew-ps = <0>; > + txd1-skew-ps = <0>; > + txd2-skew-ps = <0>; > + txd3-skew-ps = <0>; > txen-skew-ps = <0>; > - txc-skew-ps = <1560>; > + txc-skew-ps = <1860>; > rxdv-skew-ps = <0>; > - rxc-skew-ps = <1200>; > + rxc-skew-ps = <1860>; > }; > }; > }; > -- > 2.20.1 >
diff --git a/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi index db55a4ecad..44bedd8b67 100644 --- a/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi +++ b/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi @@ -20,7 +20,7 @@ }; &mmc { - u-boot,dm-pre-reloc; + status = "disabled"; }; &qspi { diff --git a/arch/arm/dts/socfpga_cyclone5_vining_fpga.dts b/arch/arm/dts/socfpga_cyclone5_vining_fpga.dts index be52fbf43d..3fb6e14372 100644 --- a/arch/arm/dts/socfpga_cyclone5_vining_fpga.dts +++ b/arch/arm/dts/socfpga_cyclone5_vining_fpga.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR X11) /* - * Copyright (C) 2015 Marek Vasut <marex@denx.de> + * Copyright (C) 2015-2019 Marek Vasut <marex@denx.de> */ #include "socfpga_cyclone5.dtsi" @@ -65,6 +65,11 @@ }; }; +&gmac0 { + status = "disabled"; + phy-mode = "gmii"; +}; + &gmac1 { status = "okay"; phy-mode = "rgmii"; @@ -84,10 +89,14 @@ rxd1-skew-ps = <0>; rxd2-skew-ps = <0>; rxd3-skew-ps = <0>; + txd0-skew-ps = <0>; + txd1-skew-ps = <0>; + txd2-skew-ps = <0>; + txd3-skew-ps = <0>; txen-skew-ps = <0>; - txc-skew-ps = <1560>; + txc-skew-ps = <1860>; rxdv-skew-ps = <0>; - rxc-skew-ps = <1200>; + rxc-skew-ps = <1860>; }; }; };
Pick minor changes from the downstream DT, disable MMC, add GMAC0 node and adjust PHY skew settings for GMAC1. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Silvio Fricke <silvio.fricke@softing.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> --- .../dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi | 2 +- arch/arm/dts/socfpga_cyclone5_vining_fpga.dts | 15 ++++++++++++--- 2 files changed, 13 insertions(+), 4 deletions(-)